专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US06452224B1 Method for manufacture of improved deep trench eDRAM capacitor and structure produced thereby 失效
标题翻译：用于制造改进的深沟槽eDRAM电容器的方法和由此产生的结构
公开(公告)号：US06452224B1
公开(公告)日：2002-09-17
申请号：US09910981
申请日：2001-07-23
申请人： Jack A. Mandelman , Carl J. Radens
发明人： Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L2994
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/945
摘要： A capacitor is formed in a trench in a well/substrate doped with a first polarity. A dielectric isolation collar formed on trench sidewalls is recessed below the trench top and is spaced from the trench bottom. Therebelow, a counterdoped plate electrode region surrounds the trench and a node dielectric covers the exposed sidewalls. A counterdoped conductive buffer layer or region covers the node dielectric. A conductive, lower diffusion barrier covers the buffer. A first polarity doped node conductor, which is formed over the lower diffusion barrier, is covered by a conductive, upper diffusion barrier. A counterdoped cap covers the upper diffusion barrier. A counterdoped strap region formed by outdiffusion into the substrate is juxtaposed with the edge of the cap.
摘要翻译：在掺杂有第一极性的阱/衬底的沟槽中形成电容器。形成在沟槽侧壁上的介电隔离套环凹陷在沟槽顶部下方并与沟槽底部间隔开。此后，反向平板电极区域围绕沟槽，并且节点电介质覆盖暴露的侧壁。反向导电缓冲层或区域覆盖节点电介质。导电的下扩散阻挡层覆盖缓冲区。形成在下部扩散阻挡层上的第一极性掺杂节点导体被导电的上扩散阻挡层覆盖。反向盖覆盖上部扩散屏障。通过向外扩散形成的对向带区域与盖的边缘并置。

62. 发明授权

US06451648B1 Process for buried-strap self-aligned to deep storage trench 失效
标题翻译：埋层自对准深沟槽工艺
公开(公告)号：US06451648B1
公开(公告)日：2002-09-17
申请号：US09233887
申请日：1999-01-20
申请人： Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： A process for forming a buried strap self-aligned to a deep storage trench. Spacers are formed on walls of a recess over a filled deep trench capacitor and a substrate. A plug is formed in a region between the spacers. Photoresist is deposited over the spacers, the plug, and material surrounding the spacers of the plug. The photoresist is patterned, thereby exposing portions of the plug, the spacers, and the surrounding material. The spacers in the surrounding material not covered by the photoresist are selectively etched, leaving a remaining portion of the spacers. The substrate and the portion of the filled deep trench exposed by the spacer removal are selectively etched. An isolation region is formed in a space created by etching of the spacers, surrounding material, substrate, and filled deep trench.
摘要翻译：一种用于形成与深存储沟槽自对准的掩埋带的工艺。垫片形成在填充的深沟槽电容器和衬底上的凹部的壁上。插塞形成在间隔件之间的区域中。光刻胶沉积在隔离物，插塞和围绕插塞间隔物的材料上。对光致抗蚀剂进行图案化，从而暴露插头，间隔件和周围材料的部分。不被光致抗蚀剂覆盖的周围材料中的间隔物被选择性地蚀刻，留下间隔物的剩余部分。通过间隔物去除暴露的衬底和填充的深沟槽的部分被选择性地蚀刻。隔离区形成在通过蚀刻间隔物，周围的材料，衬底和填充的深沟槽而产生的空间中。

63. 发明授权

US06426526B1 Single sided buried strap 失效
标题翻译：单面埋地带
公开(公告)号：US06426526B1
公开(公告)日：2002-07-30
申请号：US09870068
申请日：2001-05-30
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Gary B. Bronner , Carl J. Radens
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Gary B. Bronner , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864
摘要： An easily manufactured connecting structure from a node conductor of trench capacitor device is characterized at least in part by the presence of an isolation collar located above the node conductor, at least a portion of the collar having an exterior surface which is substantially conformal with at least a portion of an adjacent wall of the trench, a buried strap region in the trench above the node conductor, the strap region being bounded laterally by the isolation collar except at an opening in the collar. The connecting structure is preferably formed by a method involving clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench.
摘要翻译：至少部分地由位于节点导体上方的隔离套管的存在而将来自沟槽电容器装置的节点导体的容易制造的连接结构的特征在于，所述套环的至少一部分具有至少基本上保形的外表面沟槽的相邻壁的一部分，在节点导体上方的沟槽中的掩埋带区域，除了在套环的开口处之外，带区域被隔离套环侧向限定。连接结构优选地通过一种方法来形成，该方法包括在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环，同时将隔离套环留在深沟槽的其他表面。

64. 发明授权

US06426251B2 Process for manufacturing a crystal axis-aligned vertical side wall device 失效
标题翻译：用于制造晶体轴对准的垂直侧壁装置的方法
公开(公告)号：US06426251B2
公开(公告)日：2002-07-30
申请号：US09894427
申请日：2001-06-28
申请人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10876
摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.
摘要翻译：一种动态随机存取存储器（DRAM）单元，其包括具有部分地设置在沟槽的侧壁上的有源晶体管器件的深沟槽存储电容器。侧壁与具有沿着单晶轴的结晶取向的第一结晶平面对准。制造这种DRAM单元的方法包括：（a）在衬底中形成深沟槽，（b）沿着具有单晶取向的沟槽侧壁形成刻面晶体区域，以及（c）形成部分设置的晶体管器件在侧壁上的刻面晶体区域上。小面晶体区域可以通过生长氧化物环形成，例如通过局部热氧化在选择的氧化条件下，以促进沿着第一晶体轴系的较高的氧化速率而不是第二晶体轴系。

65. 发明授权

US06376324B1 Collar process for reduced deep trench edge bias 失效
标题翻译：用于减小深沟槽边缘偏置的套圈过程
公开(公告)号：US06376324B1
公开(公告)日：2002-04-23
申请号：US09602969
申请日：2000-06-23
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening , Akira Sudo
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening , Akira Sudo
IPC分类号： H01L2120
CPC分类号： H01L27/10867
摘要： Disclosed is a method to provide a new deep trench collar process which reduces encroachment of strap diffusion upon array metal oxide semiconductor field effect transistors (MOSFET's) in semiconductor devices. The invention allows a reduced effective deep trench edge bias at the top of the deep trench, without compromising storage capacitance, by maximizing the distance between the MOSFET gate conductor and the deep trench storage capacitor.
摘要翻译：公开了一种提供新的深沟槽套环工艺的方法，其减少了半导体器件中的阵列金属氧化物半导体场效应晶体管（MOSFET）上带扩散的侵入。通过使MOSFET栅极导体和深沟槽存储电容器之间的距离最大化，本发明允许在深沟槽顶部减少有效的深沟槽边缘偏压，而不损害存储电容。

66. 发明授权

US06352892B2 Method of making DRAM trench capacitor 失效
标题翻译：制造DRAM沟槽电容器的方法
公开(公告)号：US06352892B2
公开(公告)日：2002-03-05
申请号：US09764656
申请日：2001-01-17
申请人： Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： The present invention relates to a process of fabricating semiconductor memory structures, particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric constant material is incorporated into the storage node of the capacitor. Specifically, the present invention describes a process for forming deep trench storage capacitors after high temperature shallow trench isolation and gate conductor processing. This process allows for the incorporation of a temperature sensitive high dielectric constant material into the capacitor structure without causing decomposition of that material. Furthermore, the process of the present invention limits the extent of the buried-strap outdiffusion, thus improving the electrical characteristics of the array MOSFET.
摘要翻译：本发明涉及制造半导体存储器结构，特别是深沟槽半导体存储器件的工艺，其中将温度敏感的高介电常数材料并入电容器的存储节点中。具体地，本发明描述了在高温浅沟槽隔离和栅极导体处理之后形成深沟槽存储电容器的工艺。该过程允许将温度敏感的高介电常数材料并入电容器结构中而不会导致该材料的分解。此外，本发明的方法限制了埋层扩散的程度，从而改善阵列MOSFET的电特性。

67. 发明授权

US06348374B1 Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure 失效
标题翻译：具有垂直MOSFET和埋地位线导体结构的4F2 STC电池的工艺
公开(公告)号：US06348374B1
公开(公告)日：2002-02-19
申请号：US09597887
申请日：2000-06-19
申请人： Satish D. Athavale , Gary B. Bronner , Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Satish D. Athavale , Gary B. Bronner , Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/10814 , H01L27/10823 , H01L27/10885
摘要： A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.
摘要翻译：一种形成垂直晶体管的方法。在半导体衬底上形成衬垫层。通过焊盘层和半导体衬底形成槽。埋在槽中的位线形成。位线被电介质材料包围。形成延伸穿过介电材料的带，以将位线连接到半导体衬底。槽被填充在位线上方的导体。导体沿其纵向轴线切割，使得导体保持在槽的一侧。在半导体衬底之上形成基本上与位线正交的字线槽。导体的一部分在字线槽下移除，以将导体分离成单独的栅极导体。字线形成在连接到单独的栅极导体的字线槽中。

68. 发明授权

US06297086B1 Application of excimer laser anneal to DRAM processing 失效
标题翻译：准分子激光退火在DRAM处理中的应用
公开(公告)号：US06297086B1
公开(公告)日：2001-10-02
申请号：US09266337
申请日：1999-03-11
申请人： Suryanarayan G. Hegde , Kam Leung Lee , Jack A. Mandelman , Carl J. Radens
发明人： Suryanarayan G. Hegde , Kam Leung Lee , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10867
摘要： Excimer laser annealing is employed to improve the flexibility of gate activation and source/drain activation as well as to limit the extent of decomposition of a high dielectric constant storage capacitor in fabricating trench storage semiconductor memory devices.
摘要翻译：采用准分子激光退火来提高栅极激活和源极/漏极激活的灵活性，并且限制制造沟槽存储半导体存储器件中的高介电常数存储电容器的分解程度。

69. 发明授权

US06204140B1 Dynamic random access memory 有权
标题翻译：动态随机存取存储器
公开(公告)号：US06204140B1
公开(公告)日：2001-03-20
申请号：US09275337
申请日：1999-03-24
申请人： Ulrike Gruening , Jochen Beintner , Scott Halle , Jack A. Mandelman , Carl J. Radens , Juergen Wittmann , Jeffrey J. Welser
发明人： Ulrike Gruening , Jochen Beintner , Scott Halle , Jack A. Mandelman , Carl J. Radens , Juergen Wittmann , Jeffrey J. Welser
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10861
摘要： A method includes forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material. The mask has: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are selectively removing while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are selectively removed. An isolation region is formed in the removed portions of the semiconductor body. The mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material. Etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body. An insulating material is formed in the shallow trench to form a shallow trench isolation region. With such method, greater mask misalignment tolerances are permissible.
摘要翻译：一种方法包括在半导体本体中形成沟槽电容器。在电容器的上部形成凹部，该凹槽在半导体本体中具有侧壁。第一材料沉积在凹槽的侧壁和底部上方。第二种材料沉积在第一种材料上。在第二材料上提供面罩。掩模具有：掩蔽区域，以覆盖所述凹部底部的一部分; 以及位于所述凹陷侧壁的一部分上的窗口和所述凹部底部的另一部分以暴露第二材料的下面部分。第二材料的暴露的下部部分的部分是选择性地去除，同时留下基本未蚀刻的暴露的第一材料的下部。选择性地去除半导体主体的第一材料和下部的暴露部分。隔离区形成在半导体本体的去除部分中。所述掩模设置在所述第二材料上方，具有覆盖所述凹陷侧壁的一部分和所述凹部底部的一部分的掩蔽区域，以及设置在所述凹部侧壁的相对部分上方的窗口和所述凹部底部的相对部分，第二材料的部分。在半导体本体的暴露的下部设置蚀刻，以在半导体本体中形成浅沟槽。在浅沟槽中形成绝缘材料以形成浅沟槽隔离区域。通过这种方法，允许更大的掩模不对准公差。

70. 发明授权

US06184107B2 Capacitor trench-top dielectric for self-aligned device isolation 有权
标题翻译：用于自对准器件隔离的电容器沟槽电介质
公开(公告)号：US06184107B2
公开(公告)日：2001-02-06
申请号：US09271124
申请日：1999-03-17
申请人： Rama Divakaruni , Ulrike Gruening , Byeong Y. Kim , Jack A. Mandelman , Larry Nesbit , Carl J. Radens
发明人： Rama Divakaruni , Ulrike Gruening , Byeong Y. Kim , Jack A. Mandelman , Larry Nesbit , Carl J. Radens
IPC分类号： H01L2176
CPC分类号： H01L27/10867 , H01L27/10864
摘要： A semiconductor device including a substrate. At least one pair of deep trenches is arranged in the substrate. A collar lines at least a portion of a wall of each deep trench. A deep trench fill fills each deep trench. A buried strap extends completely across each deep trench over each deep trench fill and each collar. An isolation region is arranged between the deep trenches. A dielectric region overlies each buried strap in each deep trench.
摘要翻译：一种包括衬底的半导体器件。至少一对深沟槽布置在衬底中。每个深沟槽的壁的至少一部分的领子。深沟槽填充每个深沟槽。埋藏的带子完全延伸穿过每个深沟槽填充物和每个环圈的每个深沟槽。隔离区域布置在深沟槽之间。电介质区域覆盖每个深沟槽中的每个掩埋带。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式