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61. 发明申请

US20150301576A1 SYSTEM INTERCONNECT DYNAMIC SCALING BY LANE WIDTH AND OPERATING FREQUENCY BALANCING 审中-公开
公开(公告)号：US20150301576A1
公开(公告)日：2015-10-22
申请号：US14302628
申请日：2014-06-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Daniel Mark Dreps , Frank D. Ferraiolo , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3243 , Y02D10/126 , Y02D10/152
摘要： Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units have dynamically adjustable bandwidth provided by an adjustable width and adjustable operating frequency. The bandwidths may be dynamically adjusted by predicting interface bandwidth requirements. From a required bandwidth, an active width and an operating frequency for the physical link layers are determined and set. The interface is operated according to the determined width and operating frequency.

62. 发明授权

US09087135B2 Characterization and validation of processor links 有权
标题翻译：处理器链接的特征和验证
公开(公告)号：US09087135B2
公开(公告)日：2015-07-21
申请号：US14480238
申请日：2014-09-08
申请人： International Business Machines Corporation
发明人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G01R31/28 , G06F11/00 , G06F11/30 , G06F15/00 , G06F9/30 , G06F11/34 , G06F11/22 , G01R31/319
CPC分类号： G06F11/3089 , G01R31/31926 , G06F9/30 , G06F9/30007 , G06F11/22 , G06F11/221 , G06F11/3409 , G06F11/3414 , G06F11/349 , G06F15/00
摘要： A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.
摘要翻译：选择耦合第一处理器和第二处理器的处理器链接用于验证，并且识别与第一处理器和第二处理器相关联的多个通信参数设置。第一和第二处理器依次配置有每个通信参数设置。根据通信参数设置，从第一处理器向第二处理器提供一个或多个测试数据模式。至少部分地基于在第二处理器处接收到的测试数据模式来确定与所选择的处理器链路和通信参数设置相关联的性能测量。选择与最高性能测量值相关联的通信参数设置之一。所选择的通信参数设置被应用于第一和第二处理器，用于经由处理器链路在第一和第二处理器之间进行后续通信。

63. 发明申请

US20150193316A1 BUS INTERFACE OPTIMIZATION BY SELECTING BIT-LANES HAVING BEST PERFORMANCE MARGINS 审中-公开
公开(公告)号：US20150193316A1
公开(公告)日：2015-07-09
申请号：US14299319
申请日：2014-06-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Daniel Mark Dreps , Frank D. Ferraiolo , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/20
CPC分类号： G06F11/3041 , G06F11/2002 , G06F11/2007 , G06F11/2033 , G06F11/2038 , G06F11/221 , G06F11/24 , G06F11/3027 , G06F11/34 , G06F11/3409 , G06F11/3466 , G06F11/3485 , G06F11/349
摘要： A bus interface selects bit-lanes to allocate as spares by testing the performance margins of individual bit-lanes during initialization or calibration of the bus interface. The performance margins of the individual bit-lanes are evaluated as the operating frequency of the interface is increased until a number of remaining bit-lanes that meet specified performance margins is equal to the required width of the interface. The bit-lanes that do not meet the required performance margins are allocated as spares and the interface can be operated at the highest evaluated operating frequency. When an operating bit-lane fails, one of the spare bit-lanes is allocated as a replacement bit-lane and the interface operating frequency is reduced to a frequency at which the new set of operating bit-lanes meets the performance margins. The operating frequency of the interface can be dynamically increased and decreased during operation and the performance margins evaluated to optimize performance.

64. 发明授权

US09052840B2 Accessing additional memory space with multiple processors 有权
公开(公告)号：US09052840B2
公开(公告)日：2015-06-09
申请号：US13782143
申请日：2013-03-01
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , Anand Haridass , Diyanesh B. Vidyapoornachary , Robert B. Tremaine
IPC分类号： G06F12/02 , G06F3/06 , G06F9/50
CPC分类号： G06F3/067 , G06F3/167 , G06F9/5016 , G06F9/5083 , G06F12/0284
摘要： An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.

65. 发明申请

US20150005946A1 MULTIPLE LEVEL COMPUTER SYSTEM TEMPERATURE MANAGEMENT 有权
公开(公告)号：US20150005946A1
公开(公告)日：2015-01-01
申请号：US13930902
申请日：2013-06-28
申请人： International Business Machines Corporation
发明人： Anand Haridass , Prasanna Jayaraman , Tony E. Sawan
IPC分类号： G05B15/02
CPC分类号： G06F1/206 , Y02D10/16
摘要： In a method for designating cooling fan control management in a computing system, a processor causes one or more cooling fans to be managed by a first process, wherein the first process utilizes a first set of temperature sensors of a plurality of temperature sensors. A processor receives temperature data from a first set of temperature sensors. A processor determines a second process to manage the one or more cooling fans, based on the received temperature data from the first set of temperature sensors, wherein the second process utilizes a second set of temperature sensors of the plurality of temperature sensors.

66. 发明申请

US20140359310A1 SUBSYSTEM-LEVEL POWER MANAGEMENT IN A MULTI-NODE VIRTUAL MACHINE ENVIRONMENT 有权
标题翻译：多节点虚拟机环境中的子系统级电源管理
公开(公告)号：US20140359310A1
公开(公告)日：2014-12-04
申请号：US13906606
申请日：2013-05-31
申请人： International Business Machines Corporation
发明人： Anand Haridass , Prasanna Jayaraman , Tony E. Sawan
IPC分类号： G06F1/26 , G06F9/48
CPC分类号： G06F1/3206 , G06F1/324 , G06F1/3296 , G06F9/5088 , G06F9/5094 , Y02D10/126 , Y02D10/172 , Y02D10/22 , Y02D10/32
摘要： A computer-implemented method includes capping the amount of power available to each of a plurality of compute nodes, and managing power allocation among subsystems within each of the compute nodes according to the requirements of workloads assigned to each of the compute nodes. The method further comprises reporting an actual performance level and performance capability for each subsystem within each of the plurality of compute nodes, and monitoring parametric data for a particular workload. A target compute node is identified from among the compute nodes, wherein the target compute node would be capable of performing the particular workload if power was reallocated from a first subsystem to a second subsystem within the target compute node. The particular workload is then assigned to the target compute node. Optionally, assigning the particular workload may include migrating the workload to the target compute node from another of the compute nodes.
摘要翻译：计算机实现的方法包括限制多个计算节点中的每一个可用的功率量，以及根据分配给每个计算节点的工作负载的要求来管理每个计算节点内的子系统之间的功率分配。所述方法还包括报告所述多个计算节点中的每一个内的每个子系统的实际性能水平和性能能力，以及监视特定工作负载的参数数据。从计算节点中识别目标计算节点，其中如果从目标计算节点中的第一子系统重新分配到第二子系统，则目标计算节点将能够执行特定工作负载。然后将特定工作负载分配给目标计算节点。可选地，分配特定工作负载可以包括将工作负载从另一个计算节点迁移到目标计算节点。

67. 发明申请

US20140143512A1 ACCESSING ADDITIONAL MEMORY SPACE WITH MULTIPLE PROCESSORS 有权
公开(公告)号：US20140143512A1
公开(公告)日：2014-05-22
申请号：US13679496
申请日：2012-11-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Edgar R. Cordero , Anand Haridass , Diyanesh B. Vidyapoornachary , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F3/067 , G06F3/167 , G06F9/5016 , G06F9/5083 , G06F12/0284
摘要： An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.

68. 发明申请

US20140143510A1 ACCESSING ADDITIONAL MEMORY SPACE WITH MULTIPLE PROCESSORS 有权
标题翻译：使用多个处理器访问附加存储空间
公开(公告)号：US20140143510A1
公开(公告)日：2014-05-22
申请号：US13782143
申请日：2013-03-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Edgar R. Cordero , Anand Haridass , Diyanesh B. Vidyapoornachary , Robert B. Tremaine
IPC分类号： G06F3/06
CPC分类号： G06F3/067 , G06F3/167 , G06F9/5016 , G06F9/5083 , G06F12/0284
摘要： An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.
摘要翻译：提供了一种用于将附加存储器耦合到多个处理器的装置和方法。该方法可以包括确定系统中的多个处理器的存储器需求，将多个处理器的存储器要求与分配给多个处理器中的每一个的可用存储器进行比较，以及从多个处理器中选择需要额外的内存容量。该装置可以包括多个处理器，其中多个处理器耦合到逻辑元件。此外，该装置可以包括耦合到逻辑元件的附加存储器，其中逻辑元件适于从多个处理器中选择处理器以与附加存储器耦合。

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