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61. 发明申请

US20170199953A1 SENSITIVITY CALCULATION FILTERING FOR STATISTICAL STATIC TIMING ANALYSIS OF AN INTEGRATED CIRCUIT 审中-公开
公开(公告)号：US20170199953A1
公开(公告)日：2017-07-13
申请号：US14991039
申请日：2016-01-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Nathan Buck , Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Gregory M. Schaeffer , Stephen G. Shuma , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5059 , G06F2217/78 , G06F2217/84
摘要： Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In accordance with aspects of the present disclosure, a computer-implemented method for statistical static timing analysis of an integrated circuit is provided. The method may comprise identifying a timing parameter that contributes to a delay calculation. The method may further comprise determining, by a processing device, whether the identified timing parameter significantly impacts the delay calculation. The method may also comprise, responsive to determining that the identified timing parameter does not significantly impact the delay calculation, avoiding a sensitivity calculation for the identified timing parameter.

62. 发明申请

US20170193151A1 ADAPTIVE CHARACTERIZATION AND INSTANTIATION OF TIMING ABSTRACTS 有权
公开(公告)号：US20170193151A1
公开(公告)日：2017-07-06
申请号：US14986842
申请日：2016-01-04
申请人： International Business Machines Corporation
发明人： Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Dileep N. Netrabile , Stephen G. Shuma , Natesan Venkateswaran , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F2217/78 , G06F2217/84
摘要： A method, system, and computer program product to characterize and adaptively instantiate timing abstracts to perform timing analysis of an integrated circuit include generating an adaptable timing abstract for one or more macro models of a macro, the macro including two or more primitives of a component of the integrated circuit, the adaptable timing abstract being a parameterized timing model with at least one aspect represented by two or more models, and estimating requirements for the timing analysis, the requirements including accuracy, runtime, or memory requirements. Selecting a specific timing abstract, obtained by setting parameters of the adaptable timing abstract, is to perform the timing analysis based on the requirements.

63. 发明申请

US20170046307A1 RUNTIME OF CUBLAS MATRIX MULTIPLICATION ON GPU 有权
标题翻译： GPU上的CUBLAS矩阵多项式运行
公开(公告)号：US20170046307A1
公开(公告)日：2017-02-16
申请号：US14823889
申请日：2015-08-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Alexey Y. Lvov , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/16 , G06T1/20
CPC分类号： G06F17/16 , G06T1/20 , G06T2200/28
摘要： Methods for improving matrix multiplication runtimes are provided. A method includes determining, by a GPU, optimal partitions for matrix-by-matrix multiplication of two factor matrices having sizes known a priori. The determining step includes performing offline a plurality of matrix-by-matrix multiplication executions, each for a respective different combination of two-way partitions across a plurality of partition sizes. The determining step further includes determining offline a respective performance number for each of the executions based on runtime. The determining step also includes recursively repeating offline said performing and determining steps until the respective performance number ceases to improve for best-performing combinations of the two-way partitions and saving the best performing combinations of the two-way partitions as the optimal partitions. The method further includes performing online, by the GPU, the matrix-by-matrix multiplication of the two factor matrices using calls for a given one of the best performing combinations of the two-way partitions.
摘要翻译：提供了改进矩阵乘法运行时的方法。一种方法包括由GPU确定具有先验已知的尺寸的两个因子矩阵的逐矩阵乘法的最佳分区。所述确定步骤包括执行多个矩阵逐矩阵乘法执行，所述多个逐行矩阵乘法执行各自针对跨多个分区大小的双向分区的相应不同组合。所述确定步骤还包括基于运行时确定每个所述执行的脱机相应的性能编号。确定步骤还包括递归地重复离线所述执行和确定步骤，直到相应的性能编号不再改进以用于双向分区的最佳执行组合并且将双向分区的最佳执行组合保存为最佳分区。该方法还包括使用对双向分区的最佳执行组合中的给定的一个的调用，由GPU在线执行两个因子矩阵的逐矩阵乘法。

64. 发明授权

US09171124B2 Parasitic extraction in an integrated circuit with multi-patterning requirements 有权
标题翻译：具有多图案化要求的集成电路中的寄生提取
公开(公告)号：US09171124B2
公开(公告)日：2015-10-27
申请号：US14139023
申请日：2013-12-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/82
摘要： Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form.
摘要翻译：提供了用于在具有多图案化要求的集成电路的设计中提取寄生效应的系统和方法。该方法包括确定电阻解和电容解。该方法还包括执行电阻解和电容解的寄生提取以产生电阻解和电容解的平均值。该方法还包括在寄生提取期间捕获每个电阻解决方案和电容解的多图案变化源。该方法还包括确定每个捕获的变化源与相应的参数矢量的灵敏度。该方法还包括通过将每个电阻解和电容解乘以每个相应捕获的变化源的灵敏度来确定统计寄生效应。该方法还包括以矢量形式和折叠缩小矢量形式中的至少一个生成统计寄生效应作为输出。

65. 发明授权

US08839167B1 Reducing runtime and memory requirements of static timing analysis 有权
标题翻译：减少静态时序分析的运行时和内存要求
公开(公告)号：US08839167B1
公开(公告)日：2014-09-16
申请号：US13855226
申请日：2013-04-02
申请人： International Business Machines Corporation
发明人： Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table of values. The method further includes that when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis.
摘要翻译：在IC设计期间执行静态时序分析的系统和方法。提供了一种包括获得规范输入数据的方法。该方法还包括基于规范输入数据来计算至少一个输入条件标识符。该方法还包括将至少一个输入条件标识符与值表进行比较。所述方法还包括：当在所述至少一个输入条件标识符与所述值表内的至少一个值之间存在匹配时，检索与所述至少一个值相关联的先前计算的定时数据，以及将先前计算的定时数据应用于定时分析下的设计时序模型。

66. 发明申请

US20140096100A1 METHOD OF SHARING AND RE-USING TIMING MODELS IN A CHIP ACROSS MULTIPLE VOLTAGE DOMAINS 有权
标题翻译：在多个电压域中的芯片中共享和重新使用时序模型的方法
公开(公告)号：US20140096100A1
公开(公告)日：2014-04-03
申请号：US13633911
申请日：2012-10-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Debjit Sinha , Eric J. Fluhr , Stephen G. Shuma , Natesan Venkateswaran , Chandramouli Visweswariah , Michael H. Wood , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/84
摘要： A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts.
摘要翻译：考虑到制造和环境变化的VLSI电路或芯片设计的时序分析的方法和系统，其中设计包括通过共享和重新使用摘要在多于一个电压域上实例化的门或宏的多个实例。芯片的时序分析包括在抽象生成期间在不同于域的电压域中实例化的宏抽象。定时模型重新用于跨芯片电压域或芯片设计。此外，芯片设计的统计时序分析考虑了其中至少一个定时抽象模型生成时间电压域条件与芯片中的宏实例化域不同的电压域。本发明还提供共享和重新使用统计时序模型或摘要。

67. 发明授权

US08683409B2 Performing statistical timing analysis with non-separable statistical and deterministic variations 有权
标题翻译：用不可分的统计和确定性变化进行统计时序分析
公开(公告)号：US08683409B2
公开(公告)日：2014-03-25
申请号：US13768563
申请日：2013-02-15
申请人： International Business Machines Corporation
发明人： Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and slews at the corresponding corner.
摘要翻译：在一个实施例中，本发明是用于以不可分的统计和确定性变化执行统计时序分析的方法和装置。用于执行集成电路芯片的定时分析的方法的一个实施例包括计算芯片栅极和导线的延迟和压摆，其中所述延迟和压摆取决于至少一个确定性和基于角的第一工艺参数，以及第二工艺参数其与第一过程参数是统计的且不可分离的，并且使用定时数量执行单个定时运行，其中单个定时运行产生到达时间，所需的到达时间和定时偏移在输出，锁存器和电路节点集成电路芯片。计算的到达时间，所需的到达时间和定时松弛可以被投影到确定性变化的角落值，以便获得相应角落处的延迟和压摆的统计模型。

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