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    • 62. 发明授权
    • Phase change memory device using multiprogramming method
    • 相变存储器件采用多重编程方式
    • US07463511B2
    • 2008-12-09
    • US11723361
    • 2007-03-19
    • Byung-Gil ChoiChoong-Keun KwakDu-Eung KimWoo-Yeong Cho
    • Byung-Gil ChoiChoong-Keun KwakDu-Eung KimWoo-Yeong Cho
    • G11C11/00
    • G11C8/10G11C13/0004G11C13/0069G11C2013/0078G11C2213/72
    • A phase change memory device includes a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array includes a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit includes a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.
    • 相变存储器件包括存储单元阵列和写入驱动器电路以及列选择电路。 存储单元阵列包括多个块单元,每个块单元连接在相应的一对字线驱动器之间。 写驱动器电路包括多个写驱动器单元,每个写驱动器单元包括多个写驱动器,其适于向多个块单元中的相应块单元提供相应的编程电流。 列选择电路连接在存储单元阵列和写驱动器电路之间,并且适于响应于列选择信号选择多个存储器块中的至少一个,以向多个存储单元阵列中的至少一个提供对应的编程电流 的内存块。
    • 69. 发明授权
    • Semiconductor memory device having a three-dimensional cell array structure
    • 具有三维单元阵列结构的半导体存储器件
    • US07570511B2
    • 2009-08-04
    • US11755329
    • 2007-05-30
    • Woo-Yeong ChoSang-Beom KangDu-Eung Kim
    • Woo-Yeong ChoSang-Beom KangDu-Eung Kim
    • G11C11/00
    • G11C13/0023G11C11/1655G11C11/1657G11C13/0004G11C2213/71G11C2213/72
    • A semiconductor memory device includes a plurality of cell array layers including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction that intersects the first direction, and a plurality of memory cells disposed at intersections of the word lines and the bit lines. Each of the word lines has a word line position, each of the bit lines has a bit line position, and each of the memory cells includes a variable resistance device in series with a diode. The cell array layers are arranged in layers in a third direction that is perpendicular to the first and second directions. The bit lines of each of the cell array layers having a same bit line position are connected to a common column selector transistor, or the word lines of the cell array layers having a same word line position are connected to a common word line driver.
    • 半导体存储器件包括多个单元阵列层,包括沿第一方向延伸的多个字线,沿与第一方向相交的第二方向延伸的多个位线,以及设置在第一方向的交点处的多个存储单元 字线和位线。 每个字线具有字线位置,每个位线具有位线位置,并且每个存储单元包括与二极管串联的可变电阻器件。 单元阵列层在垂直于第一和第二方向的第三方向上排列成层。 具有相同位线位置的每个单元阵列层的位线连接到公共列选择晶体管,或者具有相同字线位置的单元阵列层的字线连接到公共字线驱动器。