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61. 发明申请

US20060164274A1 Cascade-type variable-order delta-sigma modulator 有权
标题翻译：级联型可变阶Δ-Σ调制器
公开(公告)号：US20060164274A1
公开(公告)日：2006-07-27
申请号：US11338651
申请日：2006-01-25
申请人： Masato Nakakita , Fumihito Inukai , Hitoshi Kobayashi
发明人： Masato Nakakita , Fumihito Inukai , Hitoshi Kobayashi
IPC分类号： H03M3/00
CPC分类号： H03M3/394 , H03M3/414
摘要： A cascade-type variable-order delta-sigma modulator with low power consumption that can change the number of stages of the quantization loops, which are connected in a cascade configuration, to an optimum number depending on peripheral circuitries in a configuration as simple as possible. The present invention includes first to nth stages of delta-sigma modulating type quantization loops (n is an integer equal to or more than 2) connected in a cascade configuration, and a noise rejecting circuit. Each quantization loop quantizes an input signal, outputs the quantization result, and feeds back the quantization result to itself. The noise rejecting circuit rejects a quantization noise of the first stage of quantization loop, and comprises (n−1) selectors for activating and de-activating the respective output signals of the second and succeeding stages of the quantization loops in compliance with the control signal.
摘要翻译：具有低功耗的级联型可变阶Δ-Σ调制器，其可以将串联配置中连接的量化循环的级数改变为最佳数量，这取决于尽可能简单的配置中的外设电路。本发明包括以级联配置连接的Δ-Σ调制型量化环（n为等于或大于2的整数）的第一至第N级，以及噪声抑制电路。每个量化环对输入信号进行量化，输出量化结果，并将量化结果反馈给自身。噪声抑制电路拒绝量化环路的第一级的量化噪声，并且包括用于根据控制信号激活和去激活量化环路的第二级和后级的各个输出信号的（n-1）个选择器。

62. 发明申请

US20060153764A1 Pyrogenically produced silicone dioxide powder 有权
标题翻译：热解产生的二氧化硅粉末
公开(公告)号：US20060153764A1
公开(公告)日：2006-07-13
申请号：US11085151
申请日：2005-03-22
申请人： Kai Schumacher , Naruyasu Ishibashi , Hitoshi Kobayashi , Paul Brandl
发明人： Kai Schumacher , Naruyasu Ishibashi , Hitoshi Kobayashi , Paul Brandl
IPC分类号： C01B33/12
CPC分类号： C01B33/183 , Y10T428/2982
摘要： Pyrogenically produced silicon dioxide powder in the form of aggregates of primary particles having a BET surface area of 300±25 m2/g, wherein the aggregates display an average surface area of 4800 to 6000 nm2, an average equivalent circle diameter (ECD) of 60 to 80 nm and an average circumference of 580 to 750 nm. It is produced by a pyrogenic process in which silicon tetrachloride and a maximum of up to 40 wt. % of a second silicon component comprising H3SiCl, H2SiCl2, HSiCl3, CH3SiCl3, (CH3)2SiCl2, (CH3)3SiCl and/or (n-C3H7)SiCl3 are mixed with primary air and a combustion gas and burnt into a reaction chamber, secondary air also being introduced into the reaction chamber, and the feed materials being chosen such that an adiabatic flame temperature of 1390 to 1450° C. is obtained. It can be used as a filler.
摘要翻译：以BET表面积为300±25m 2 / g的一次粒子的聚集体形式的热解生成的二氧化硅粉末，其中聚集体的平均表面积为4800〜6000nm， 2，平均当量圆直径（ECD）为60〜80nm，平均周长为580〜750nm。它是通过热解法生产的，其中四氯化硅和最多达40wt。％的包含H 3 SiCl，H 2 SiCl 2，HSiCl 3，CH，SUB的第二硅组分的％（CH 3）3 SiCl 3，（CH 3 3）2 SiCl 2，（CH 3） 3 N 3 SiCl 3和/或（n C 3 H 7）SiCl 3 3与初级空气和燃烧气体并燃烧到反应室中，二次空气也被引入反应室，并且进料选择为使得绝热火焰温度为1390至1450℃。它可以用作填料。

63. 发明申请

US20060145290A1 Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type 审中-公开
公开(公告)号：US20060145290A1
公开(公告)日：2006-07-06
申请号：US11294411
申请日：2005-12-06
申请人： Hideki Okumura , Hitoshi Kobayashi , Masanobu Tsuchitani , Akihiko Osawa , Wataru Saito , Masakazu Yamaguchi , Ichiro Omura
发明人： Hideki Okumura , Hitoshi Kobayashi , Masanobu Tsuchitani , Akihiko Osawa , Wataru Saito , Masakazu Yamaguchi , Ichiro Omura
IPC分类号： H01L29/00 , H01L21/425 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/7802
摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

64. 发明申请

US20060138536A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060138536A1
公开(公告)日：2006-06-29
申请号：US11151410
申请日：2005-06-14
申请人： Shigeo Kouzuki , Hideki Okumura , Wataru Saito , Masaru Izumisawa , Masahiko Shiomi , Hitoshi Kobayashi , Kenichi Tokano , Satoshi Yanagisawa , Hironori Yoshioka , Manabu Kimura
发明人： Shigeo Kouzuki , Hideki Okumura , Wataru Saito , Masaru Izumisawa , Masahiko Shiomi , Hitoshi Kobayashi , Kenichi Tokano , Satoshi Yanagisawa , Hironori Yoshioka , Manabu Kimura
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/66712 , H01L29/7811
摘要： A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.
摘要翻译：提供第一导电类型的半导体衬底作为用于多个功率MISFET单元的公共漏极。在半导体衬底上形成中间半导体层，其杂质浓度低于半导体衬底的杂质浓度。柱状区域形成在中间半导体层上，并且包括具有比中间半导体层的杂质浓度低的第一导电类型的半导体区域。

65. 发明申请

US20060081903A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060081903A1
公开(公告)日：2006-04-20
申请号：US11249265
申请日：2005-10-14
申请人： Tomoki Inoue , Satoshi Aida , Yasushi Takahashi , Hitoshi Kobayashi
发明人： Tomoki Inoue , Satoshi Aida , Yasushi Takahashi , Hitoshi Kobayashi
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L21/76224 , H01L29/42368 , H01L29/51 , H01L29/515 , H01L29/66348 , H01L29/66734 , H01L29/7397
摘要： An n channel type power MOS field effect transistor has silica particles buried in a bottom portion of a trench and a gate electrode buried in another portion of the trench. The gate electrode is in contact with the silica particles. A gap of the silica particles is not filled with the gate electrode.
摘要翻译： n沟道型功率MOS场效应晶体管具有掩埋在沟槽的底部的二氧化硅颗粒和埋在沟槽的另一部分中的栅电极。栅电极与二氧化硅颗粒接触。二氧化硅颗粒的间隙没有被栅电极填充。

66. 发明授权

US06995426B2 Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type 有权
标题翻译：具有垂直金属绝缘体半导体晶体管的半导体器件具有不同导电类型的多个空间重叠区域
公开(公告)号：US06995426B2
公开(公告)日：2006-02-07
申请号：US10327937
申请日：2002-12-26
申请人： Hideki Okumura , Hitoshi Kobayashi , Masanobu Tsuchitani , Akihiko Osawa , Wataru Saito , Masakazu Yamaguchi , Ichiro Omura
发明人： Hideki Okumura , Hitoshi Kobayashi , Masanobu Tsuchitani , Akihiko Osawa , Wataru Saito , Masakazu Yamaguchi , Ichiro Omura
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/7802
摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.
摘要翻译：半导体器件包括形成在第一导电类型的半导体层中的扩散区域。扩散区域分别包括第一和第二导电类型的第一和第二杂质扩散区域。扩散区域具有由第一和第二杂质扩散区域的杂质浓度限定的第一和第二区域。第一和第二区域之间的结点形成在第一和第二杂质扩散区域彼此重叠的部分中。在第一或第二区域的半导体层的平面方向上的杂质浓度的周期小于半导体层的平面方向上的构成第一或第二区域的第一和第二杂质扩散区域的最大宽度第二区。

67. 发明授权

US06825712B2 Filter circuit, front end of communication system including the filter circuit, and communication device including the same 失效
标题翻译：滤波电路，包括滤波电路的通信系统的前端，以及包括该滤波电路的通信装置
公开(公告)号：US06825712B2
公开(公告)日：2004-11-30
申请号：US10385427
申请日：2003-03-12
申请人： Shiro Dosho , Takashi Morie , Hitoshi Kobayashi , Norihide Kinugasa , Masaomi Toyama
发明人： Shiro Dosho , Takashi Morie , Hitoshi Kobayashi , Norihide Kinugasa , Masaomi Toyama
IPC分类号： H03K500
CPC分类号： H03H11/04
摘要： In a front end that has a filter circuit and is used for a communication system having an asymmetric communication channel in which upstream and downstream data rates are different, a filter circuit for received signals, which is for filtering received signals, and a filter circuit for transmitted signals, which is for filtering transmitted signals, are provided. The filter circuit for received signals has an amplifier block including a plurality of amplifiers, a capacitor block including a plurality of capacitors and being connected to the plurality of amplifiers included in the amplifier block, and a first and a second resistor blocks each including a plurality of resistors. Either one of the first or the second resistor block is selectively switched so as to be connected to the amplifier block by a resistor block-switching circuit. The circuit scale is reduced since only one amplifier block and one capacitor block are commonly used for two kinds of filter circuits.
摘要翻译：在具有滤波器电路的前端中，用于具有上行和下行数据速率不同的非对称通信信道的通信系统，用于对接收信号进行滤波的接收信号的滤波电路和用于提供用于滤波发送信号的发送信号。用于接收信号的滤波器电路具有包括多个放大器的放大器模块，包括多个电容器并且连接到放大器模块中所包括的多个放大器的电容器模块，以及包括多个放大器的第一和第二电阻块的电阻。选择性地切换第一或第二电阻器块中的任何一个，以便通过电阻器块切换电路连接到放大器块。由于只有一个放大器块和一个电容器块通常用于两种滤波器电路，电路规模减小。

68. 发明授权

US06808811B1 Protecting film for polarizing plate and polarizing plate 失效
标题翻译：防偏光板和偏光板保护膜
公开(公告)号：US06808811B1
公开(公告)日：2004-10-26
申请号：US09856162
申请日：2001-09-21
申请人： Takahiko Sawada , Yasumasa Okada , Hitoshi Kobayashi
发明人： Takahiko Sawada , Yasumasa Okada , Hitoshi Kobayashi
IPC分类号： B32B2740
CPC分类号： B32B7/12 , B32B27/08 , B32B27/30 , B32B2375/00 , C08J7/04 , C08J7/047 , C08J2365/00 , C08J2475/00 , G02B1/105 , G02B1/111 , G02B1/14 , G02B1/16 , G02B5/3033 , Y10T428/10 , Y10T428/1041 , Y10T428/1082 , Y10T428/31573 , Y10T428/31587
摘要： The polarizing plate protection film of the present invention has excellent adhesion with the polarizer because of the polyurethane resin layer formed on the thermoplastic saturated norbornene-type resin film. In addition, blocking of the protection film can be prevented by the PVA layer formed on the polyurethane resin layer. The polarizing plate using the protection film of the present invention is excellent in terms of durability under high temperature and high humidity conditions, and it is suitably used for liquid crystal displays and such.
摘要翻译：由于在热塑性饱和降冰片烯类树脂膜上形成聚氨酯树脂层，本发明的偏振片保护膜与偏振片具有优异的粘附性。此外，通过在聚氨酯树脂层上形成的PVA层可以防止保护膜的堵塞。使用本发明的保护膜的偏光板在高温高湿条件下的耐久性优异，适合用于液晶显示器等。

69. 发明申请

US20190027744A2 NEGATIVE ELECTRODE COMPOSITION FOR ELECTRIC STORAGE DEVICE, NEGATIVE ELECTRODE INCLUDING THE COMPOSITION, ELECTRIC STORAGE DEVICE, AND METHOD FOR PRODUCING NEGATIVE ELECTRODE FOR ELECTRIC STORAGE DEVICE 审中-公开
公开(公告)号：US20190027744A2
公开(公告)日：2019-01-24
申请号：US15526707
申请日：2015-11-12
申请人： Shinichi Maruyama , Koji Nitta , Shoichiro Sakai , Atsushi Fukunaga , Eiko Imazaki , Koma Numata , Hideaki Ito , Hitoshi Kobayashi , Toshiaki Yamashita , Shinichi Maruyama
发明人： Koji Nitta , Shoichiro Sakai , Atsushi Fukunaga , Eiko Imazaki , Koma Numata , Hideaki Ito , Hitoshi Kobayashi , Toshiaki Yamashita , Shinichi Maruyama
IPC分类号： H01M4/38 , H01M10/0564
CPC分类号： H01M4/381 , H01G11/04 , H01G11/30 , H01G11/62 , H01G11/86 , H01M4/0459 , H01M4/134 , H01M4/1395 , H01M4/362 , H01M10/054 , H01M10/0564 , H01M10/0566 , Y02E60/13
摘要： Provided is a method for producing a negative electrode for an electric storage device, the method comprising the steps of: preparing a negative electrode composition comprising a negative electrode active material that reversibly carries a sodium ion, metal sodium, and a liquid dispersion medium for dispersing them; allowing a negative electrode current collector to hold the negative electrode composition; evaporating at least part of the liquid dispersion medium from the negative electrode composition held by the negative electrode current collector, thereby giving a negative electrode precursor comprising the negative electrode active material, the metal sodium, and the negative electrode current collector; and bringing the negative electrode precursor into contact with an electrolyte having sodium ion conductivity, thereby doping the negative electrode active material with sodium eluted from the metal sodium.

70. 发明授权

US09978197B2 Banknote handling apparatus 有权
公开(公告)号：US09978197B2
公开(公告)日：2018-05-22
申请号：US14000687
申请日：2012-02-20
申请人： Hitoshi Kobayashi , Shingo Hashimoto , Kazuhiko Takahashi
发明人： Hitoshi Kobayashi , Shingo Hashimoto , Kazuhiko Takahashi
IPC分类号： G07F7/04 , G07D11/00
CPC分类号： G07D11/00 , G07D11/0006 , G07D11/0009 , G07D11/0018 , G07D11/0057 , G07D11/006 , G07D11/0066 , G07D11/0084
摘要： In a banknote handling apparatus capable of dealing with a depositing/dispensing process by a banknote cassette and a manual depositing/dispensing process, the banknote handling apparatus enables a depositing process without dispensing a reject banknote, which has been deposited from the banknote cassette, to the outside. A banknote accounting apparatus 22 capable of receiving a banknote from banknote feeding units (a banknote receiving unit 201a, a banknote cassette 30a) includes: a transport unit 230a configured such that the banknote feeding unit is connected thereto, the transport unit configured to transport a received banknote; a recognition unit 240a configured to recognize the banknote being transported; an apparatus-internal reject unit 224a configured to store a reject banknote inside the apparatus; an apparatus-external reject unit 22a configured to dispense a reject banknote outside the apparatus; a unit deciding part configured to decide the banknote feeding unit for feeding a banknote; and a control unit configured to decide, when the recognition unit recognizes a banknote having been received from the banknote feeding unit as a reject banknote, to which one of the apparatus-internal reject unit 224a and the apparatus-external reject unit 222a the reject banknote is transported, based on the banknote feeding unit having fed the banknote.

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