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61. 发明授权

US08937361B2 BSI image sensor package with variable-height silicon for even reception of different wavelengths 有权
标题翻译： BSI图像传感器封装，具有可变高度的硅，用于均匀接收不同的波长
公开(公告)号：US08937361B2
公开(公告)日：2015-01-20
申请号：US13114243
申请日：2011-05-24
申请人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
发明人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
IPC分类号： H01L31/0232 , H01L27/146
CPC分类号： H01L27/14625 , H01L27/1461 , H01L27/14629 , H01L27/14632 , H01L27/1464 , H01L27/14645 , H01L27/14687
摘要： A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a rear face. A semiconductor region has a first thickness between the first light sensing element and the rear face and a second thickness between the second light sensing element and the rear face such that the first and second light sensing elements receive light of substantially the same intensity. A dielectric region is provided at least substantially filling a space of the semiconductor region adjacent at least one of the light sensing elements. The dielectric region may include at least one light guide.
摘要翻译：提供了一种用于背面照明的微电子图像传感器组件及其制造方法。该组件包括具有在正面暴露的触点的微电子元件和被布置成通过后表面接收不同波长的光的光感测元件。半导体区域在第一光感测元件和后表面之间具有第一厚度，并且在第二光感测元件和后表面之间具有第二厚度，使得第一和第二光感测元件接收基本上相同强度的光。提供至少基本上填充与至少一个光感测元件相邻的半导体区域的空间的电介质区域。电介质区域可以包括至少一个光导。

62. 发明授权

US08916781B2 Cavities containing multi-wiring structures and devices 有权
标题翻译：包含多层结构和设备的腔
公开(公告)号：US08916781B2
公开(公告)日：2014-12-23
申请号：US13296785
申请日：2011-11-15
申请人： Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Cyprian Emeka Uzoh
发明人： Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Cyprian Emeka Uzoh
IPC分类号： H05K1/11 , H05K1/03 , H05K1/09 , H05K1/00 , H01L23/498 , H01R12/71 , H05K3/42
CPC分类号： H05K1/0271 , H01L23/49827 , H01L2924/0002 , H01R12/714 , H05K1/114 , H05K1/115 , H05K3/42 , H05K2201/09645 , H05K2201/10378 , H05K2203/0242 , H05K2203/025 , Y10T29/49165 , H01L2924/00
摘要： An interconnection component includes an element with an opening, a plurality of conductors electrically insulted from one another extending through the opening, and a plurality of second contacts electrically insulated from one another. The element is comprised of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. At least some of the conductors extend along at least one inner surface of the opening. The conductors define a plurality of wettable first contacts at the first surface. The first contacts are at least partially aligned with the opening in a direction of the thickness and electrically insulated from one another.
摘要翻译：互连部件包括具有开口的元件，延伸穿过开口彼此电绝缘的多个导体以及彼此电绝缘的多个第二触点。该元件由热膨胀系数小于10ppm /℃的材料构成。至少一些导体沿开口的至少一个内表面延伸。导体在第一表面限定多个可润湿的第一接触。第一触点在厚度方向上与开口至少部分地对齐，并且彼此电绝缘。

63. 发明授权

US08652935B2 Void-free wafer bonding using channels 有权
标题翻译：使用通道的无空隙晶片接合
公开(公告)号：US08652935B2
公开(公告)日：2014-02-18
申请号：US12970529
申请日：2010-12-16
申请人： Ilyas Mohammed , Piyush Savalia , Craig Mitchell , Vage Oganesian , Belgacem Haba
发明人： Ilyas Mohammed , Piyush Savalia , Craig Mitchell , Vage Oganesian , Belgacem Haba
IPC分类号： H01L21/30
CPC分类号： H01L23/562 , B81C1/00269 , B81C1/00357 , H01L21/2007 , H01L21/561 , H01L21/563 , H01L21/568 , H01L23/13 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L29/0657 , H01L2224/29186 , H01L2224/2919 , H01L2224/32057 , H01L2224/32145 , H01L2224/32225 , H01L2224/83051 , H01L2224/83191 , H01L2224/83345 , H01L2224/83385 , H01L2224/83855 , H01L2224/83856 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06575 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/014 , H01L2924/0665 , H01L2924/10158 , H01L2924/10253 , H01L2924/1027 , H01L2924/1032 , H01L2924/1037 , H01L2924/14 , H01L2924/1461 , H01L2924/3511 , H01L2224/83 , H01L2924/00
摘要： A method of bonding first and second microelectronic elements includes pressing together a first substrate containing active circuit elements therein with a second substrate, with a flowable dielectric material between confronting surfaces of the respective substrates, each of the first and second substrates having a coefficient of thermal expansion less than 10 parts per million/° C., at least one of the confronting surfaces having a plurality of channels extending from an edge of such surface, such that the dielectric material between planes defined by the confronting surfaces is at least substantially free of voids and has a thickness over one micron, and at least some of the dielectric material flows into at least some of the channels.
摘要翻译：接合第一和第二微电子元件的方法包括将含有有源电路元件的第一衬底与第二衬底压在一起，在相应衬底的相对表面之间具有可流动介电材料，第一和第二衬底中的每一个具有热系数膨胀小于10ppm /℃，至少一个相对表面具有从该表面的边缘延伸的多个通道，使得由相对表面限定的平面之间的电介质材料至少基本上不含空隙并且具有超过一微米的厚度，并且至少一些介电材料流入至少一些通道。

64. 发明授权

US08610259B2 Multi-function and shielded 3D interconnects 有权
标题翻译：多功能和屏蔽3D互连
公开(公告)号：US08610259B2
公开(公告)日：2013-12-17
申请号：US12884695
申请日：2010-09-17
申请人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia
发明人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia
IPC分类号： H01L23/48
CPC分类号： H01L23/49827 , H01L21/6835 , H01L23/481 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/06 , H01L2221/68327 , H01L2221/6834 , H01L2223/6622 , H01L2224/05009 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/0557 , H01L2224/05644 , H01L2224/05647 , H01L2224/06181 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15788 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.
摘要翻译：微电子单元包括基本上由半导体材料组成的半导体元件，其具有前表面，后表面，与前表面相邻的多个有源半导体器件，在前表面暴露的多个导电焊盘，以及延伸穿过半导体元件。至少一个导电焊盘可以至少部分地覆盖开口并且可以与至少一个有源半导体器件电连接。微电子单元还可以包括暴露在后表面处以与外部部件连接的第一导电元件，第一导电元件延伸穿过开口并与至少一个导电焊盘电连接，第二导电元件延伸穿过开口并与第一导电元件绝缘。至少一个导电焊盘可以覆盖在第二导电元件的周边边缘上。

65. 发明授权

US08512491B2 Dual wafer spin coating 有权
标题翻译：双晶圆片旋涂
公开(公告)号：US08512491B2
公开(公告)日：2013-08-20
申请号：US12974611
申请日：2010-12-21
申请人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
发明人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
IPC分类号： B32B41/00
CPC分类号： H01L22/12 , H01L21/67092
摘要： A method of bonding a first substrate and a second substrate includes the steps of rotating first substrate with an adhesive mass thereon, and second substrate contacting the mass and overlying the first substrate, controlling a vertical height of a heated control platen spaced apart from and not contacting the second substrate so as to control a temperature of the adhesive mass, so as to at least one of bond the first and second substrates in alignment with one another, or achieve a sufficiently planar adhesive interface between the first and second substrates.
摘要翻译：接合第一基板和第二基板的方法包括以下步骤：使第一基板与其上的粘合剂质量物质旋转，第二基板接触物料并覆盖第一基板，控制加热的控制台板的垂直高度，使所述第二基板接触以控制所述粘合剂物料的温度，以便使所述第一和第二基板彼此对准的至少一个接合，或在所述第一和第二基板之间实现足够平坦的粘合界面。

66. 发明授权

US08476774B2 Off-chip VIAS in stacked chips 有权
标题翻译：芯片中的离散VIAS堆叠芯片
公开(公告)号：US08476774B2
公开(公告)日：2013-07-02
申请号：US13316890
申请日：2011-12-12
申请人： Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
发明人： Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/78 , H01L21/6835 , H01L23/5382 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68377 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/9202 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2224/82 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.
摘要翻译：微电子组件包括第一和第二堆叠的微电子元件，每个微电子元件具有沿前表面延伸并且至少其第一边缘延伸的间隔开的迹线。绝缘区域可以接触每个微电子元件的边缘，并且每个微电子元件的迹线的至少部分延伸超过相应的第一边缘。绝缘区域可以限定与微电子元件的第一和第二边缘相邻的第一和第二侧表面。多个间隔开的开口可以沿着微电子组件的侧表面延伸。与相应迹线连接的电导体可以具有设置在相应开口中并沿相应开口延伸的部分。电导体可以延伸到覆盖在微电子元件中的一个的表面上的焊盘或焊球。

67. 发明申请

US20130122747A1 CAVITIES CONTAINING MULTI-WIRING STRUCTURES AND DEVICES 有权
标题翻译：包含多层结构和设备的CAVITIES
公开(公告)号：US20130122747A1
公开(公告)日：2013-05-16
申请号：US13296785
申请日：2011-11-15
申请人： Cyprian Uzoh , Craig Mitchell , Belgacem Haba , Ilyas Mohammed
发明人： Cyprian Uzoh , Craig Mitchell , Belgacem Haba , Ilyas Mohammed
IPC分类号： H01R24/28
CPC分类号： H05K1/0271 , H01L23/49827 , H01L2924/0002 , H01R12/714 , H05K1/114 , H05K1/115 , H05K3/42 , H05K2201/09645 , H05K2201/10378 , H05K2203/0242 , H05K2203/025 , Y10T29/49165 , H01L2924/00
摘要： An interconnection component includes an element with an opening, a plurality of conductors electrically insulted from one another extending through the opening, and a plurality of second contacts electrically insulated from one another. The element is comprised of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. At least some of the conductors extend along at least one inner surface of the opening. The conductors define a plurality of wettable first contacts at the first surface. The first contacts are at least partially aligned with the opening in a direction of the thickness and electrically insulated from one another.
摘要翻译：互连部件包括具有开口的元件，延伸穿过开口彼此电绝缘的多个导体以及彼此电绝缘的多个第二触点。该元件由热膨胀系数小于10ppm /℃的材料构成。至少一些导体沿开口的至少一个内表面延伸。导体在第一表面限定多个可润湿的第一接触。第一触点在厚度方向上与开口至少部分地对齐，并且彼此电绝缘。

68. 发明申请

US20130010441A1 MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION 有权
公开(公告)号：US20130010441A1
公开(公告)日：2013-01-10
申请号：US13618514
申请日：2012-09-14
申请人： Vage Oganesian , Belgacem Haba , Craig Mitchell , Ilyas Mohammed , Piyush Savalia
发明人： Vage Oganesian , Belgacem Haba , Craig Mitchell , Ilyas Mohammed , Piyush Savalia
IPC分类号： H05K1/18 , H05K5/00
CPC分类号： H01L21/76819 , H01L21/76877 , H01L23/13 , H01L23/3128 , H01L23/49827 , H01L23/4985 , H01L23/5389 , H01L24/18 , H01L24/19 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/97 , H01L25/105 , H01L25/117 , H01L25/16 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16235 , H01L2224/24227 , H01L2224/24247 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/82 , H01L2224/92244 , H01L2224/97 , H01L2225/1023 , H01L2225/1029 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01061 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/07811 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15156 , H01L2924/15165 , H01L2924/15192 , H01L2924/15311 , H01L2924/15313 , H01L2924/15331 , H01L2924/157 , H01L2924/15788 , H01L2924/18161 , Y10T29/49002 , H01L2224/81 , H01L2924/00 , H01L2224/83
摘要： A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.

69. 发明申请

US20120273933A1 THREE-DIMENSIONAL SYSTEM-IN-A-PACKAGE 有权
标题翻译：三维系统包装
公开(公告)号：US20120273933A1
公开(公告)日：2012-11-01
申请号：US13097943
申请日：2011-04-29
申请人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
发明人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
IPC分类号： H01L23/12 , H01L21/58 , H01L23/488
CPC分类号： H01L25/50 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2225/06524 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/00
摘要： A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having a minimum thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.
摘要翻译：微电子组件可以包括例如电介质或半导体材料的第一，第二和第三堆叠的基本平坦的元件，并且其可以具有小于10ppm /℃的CTE。组件可以是微电子封装，并且可以并入有源半导体在第一，第二或第三元件中的一个，两个或更多个元件中的装置可以协同地作为系统级封装。在一个示例中，具有最小厚度小于10微米的导电元件可以通过电镀形成，并且可以电连接第一，第二或第三元件中的两个或更多个。导电元件可以完全位于另一个基本上平面的元件的表面之下。

70. 发明申请

US20120267751A1 INTERPOSER HAVING MOLDED LOW CTE DIELECTRIC 有权
标题翻译：具有成型低CTE电介质的插件
公开(公告)号：US20120267751A1
公开(公告)日：2012-10-25
申请号：US13091800
申请日：2011-04-21
申请人： Belgacem Haba , Ilyas Mohammed
发明人： Belgacem Haba , Ilyas Mohammed
IPC分类号： H01L23/482 , H01L27/02 , H01L21/28
CPC分类号： H01L21/486 , H01L23/49827 , H01L23/49861 , H01L23/49894 , H01L2224/16225 , H01L2924/09701 , H01L2924/15311 , H05K3/4046 , H05K2201/0979 , H05K2201/10378 , H05K2201/10674
摘要： A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.
摘要翻译：公开了一种用于制造互连部件的方法，包括形成远离参考表面延伸的多个金属柱。每个柱形成具有一对相对的端面和在它们之间延伸的边缘表面。形成接触边缘表面和相邻柱之间的填充空间的电介质层。电介质层具有邻近第一和第二端面的第一和第二相对表面。电介质层的热膨胀系数小于8ppm /℃。互连部件完成，使得它们在横向方向上延伸的柱的第一和第二端面之间没有互连。第一和第二多个可湿接触部分邻近第一和第二相对表面。可湿接触可用于将互连部件连接到微电子元件或电路板。

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