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61. 发明授权

US07791962B2 Semiconductor device and semiconductor signal processing apparatus 失效
标题翻译：半导体装置及半导体信号处理装置
公开(公告)号：US07791962B2
公开(公告)日：2010-09-07
申请号：US12213131
申请日：2008-06-16
申请人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
发明人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
IPC分类号： G11C7/10
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译：存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

62. 发明申请

US20090113122A1 CONTENT ADDRESSABLE MEMORY DEVICE HAVING MATCH LINE EQUALIZER CIRCUIT 有权
标题翻译：具有匹配线路均衡器电路的内容可寻址存储器件
公开(公告)号：US20090113122A1
公开(公告)日：2009-04-30
申请号：US12261598
申请日：2008-10-30
申请人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
发明人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
IPC分类号： G06F12/00 , G06F17/30
CPC分类号： G06F17/30982 , G11C15/04 , Y02D10/45
摘要： In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other.
摘要翻译：在内容可寻址存储器件中，在分别连接到第一和第二匹配线的两个TCAM单元中的搜索操作之前，存储器控制器将第一匹配线连接到电源，并将第二匹配线连接到地，然后将第一和第二匹配线彼此之间，使得第一和第二匹配线的电位彼此相同。

63. 发明申请

US20060285576A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060285576A1
公开(公告)日：2006-12-21
申请号：US11452317
申请日：2006-06-14
申请人： Takayuki Gyoten , Fukashi Morishita , Katsumi Dosaka
发明人： Takayuki Gyoten , Fukashi Morishita , Katsumi Dosaka
IPC分类号： G01K7/00 , H05B1/02
CPC分类号： G01K7/01
摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.
摘要翻译：提供了能够高精度地检测半导体器件的温度的技术。检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。

64. 发明授权

US06614713B2 Semiconductor memory device having a circuit for fast operation 有权
标题翻译：具有用于快速操作的电路的半导体存储器件
公开(公告)号：US06614713B2
公开(公告)日：2003-09-02
申请号：US09922670
申请日：2001-08-07
申请人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
发明人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
IPC分类号： G11C800
CPC分类号： G11C29/48 , G11C11/406
摘要： A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.
摘要翻译：半导体存储器件包括命令解码器，接收外部信号并发出命令，时钟缓冲器接收外部时钟，门和刷新计数器。当测试信号处于L电平时，根据命令解码器的输出发出自动刷新信号。当测试信号为H电平时，根据时钟缓冲器的输出（外部时钟）发出自动刷新信号。因此，即使通过低速测试仪，也可以以良好的定时精度进行测试。

65. 发明授权

US06597599B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06597599B2
公开(公告)日：2003-07-22
申请号：US10188977
申请日：2002-07-05
申请人： Toshinori Morihara , Hiroki Shimano , Katsumi Dosaka , Kazutami Arimoto
发明人： Toshinori Morihara , Hiroki Shimano , Katsumi Dosaka , Kazutami Arimoto
IPC分类号： G11C1124
CPC分类号： H01L27/10805 , H01L27/0207 , H01L27/10897
摘要： In a semiconductor memory in which memory cells where a bit line is connected with the impurity diffused area of MOS transistors are arranged in a close packed layout in order to reduce the gate capacitance and junction capacitance of the impurity diffused area of the MOS transistor, the width W1 of the active region of the MOS transistor of field pattern FL constituting the memory cell is formed narrower than the width W2 of the active region of the capacitor.
摘要翻译：在半导体存储器中，其中位线与MOS晶体管的杂质扩散区域连接的存储器单元以紧密堆积布置布置，以便降低MOS晶体管的杂质扩散区域的栅极电容和结电容，构成存储单元的场图案FL的MOS晶体管的有源区域的宽度W1形成为比电容器的有源区域的宽度W2窄。

66. 发明授权

US06400628B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06400628B2
公开(公告)日：2002-06-04
申请号：US09748139
申请日：2000-12-27
申请人： Katsumi Dosaka , Hiroki Shimano , Hiroki Sugano , Kazutami Arimoto
发明人： Katsumi Dosaka , Hiroki Shimano , Hiroki Sugano , Kazutami Arimoto
IPC分类号： G11C702
CPC分类号： H01L27/10882 , G11C7/12 , G11C7/14 , G11C7/18 , H01L27/10885 , H01L27/10894
摘要： A dummy bit line is formed from the same layer as and separately from a bit line, and is running in parallel with the bit line. Capacitor is formed on the layer upper than bit line and has a cell plate. An intermediate interconnection is formed on the layer upper than capacitor and is electrically connected to cell plate and dummy bit line. Thus, a semiconductor memory device is obtained in which a cell plate voltage can reliably be fed to a cell plate while preventing the increase of the area of a chip.
摘要翻译：虚位线与位线相同层分开形成，与位线并行运行。电容器形成在比位线上方的层上并且具有单元板。中间互连形成在电容层上方，电连接到单元板和虚拟位线。因此，获得半导体存储器件，其中可以可靠地将电池板电压馈送到电池板，同时防止芯片面积的增加。

67. 发明授权

US06373774B1 Semiconductor memory device with bank configuration 有权
公开(公告)号：US06373774B1
公开(公告)日：2002-04-16
申请号：US09773710
申请日：2001-02-02
申请人： Masatoshi Ishikawa , Katsumi Dosaka
发明人： Masatoshi Ishikawa , Katsumi Dosaka
IPC分类号： G11C800
摘要： The semiconductor memory device includes a logic circuit and a memory macro. The memory macro has a region in which memory blocks are formed. Memory spaces are increased in a predetermined order. Address connection lines connecting between the logic circuit and the memory macro alter a connecting relation such that consecutive addresses are realized in each bank. A word line address specified by the logic circuit is used in the memory macro with no change therein.

68. 发明授权

US6091659A Synchronous semiconductor memory device with multi-bank configuration 失效
标题翻译：具有多组配置的同步半导体存储器件
公开(公告)号：US6091659A
公开(公告)日：2000-07-18
申请号：US318433
申请日：1999-05-25
申请人： Naoya Watanabe , Katsumi Dosaka
发明人： Naoya Watanabe , Katsumi Dosaka
IPC分类号： G11C11/407 , G11C7/10 , G11C8/16 , G11C11/401 , G11C11/409 , G11C8/00
CPC分类号： G11C8/16 , G11C7/1006
摘要： Memory blocks provided to share a sense amplifier band, a global IO (GIOB) bus provided in common to the memory blocks for transferring internal data, and local IO bus lines provided corresponding to the memory blocks are connection-controlled based on signals related to a column select operation. Driving memory blocks independently from each other permits each memory block to be used as a bank, and if one memory block is accessed during activation of another memory block, data can be prevented from colliding on the global IO bus. A main memory with high page hit rate is implemented using a semiconductor memory device with a shared-sense amplifier configuration. When a memory block sharing a sense amplifier coupled to another memory block is addressed, the another memory block is inactivated and then addressed memory block is accessed, when a valid data is output, such valid data outputting is signaled by a data valid signal.
摘要翻译：提供用于共享读出放大器频带的存储器块，共同提供用于传送内部数据的存储器块的全局IO（GIOB）总线以及与存储器块相对应地提供的本地IO总线的连接控制是基于与列选择操作。彼此独立地驱动存储器块允许每个存储器块用作存储体，并且如果在激活另一个存储器块期间访问一个存储器块，则可以防止数据在全局IO总线上冲突。具有高页命中率的主存储器使用具有共享读出放大器配置的半导体存储器件来实现。当共享耦合到另一个存储器块的读出放大器的存储器块被寻址时，另一个存储块被去激活，然后寻址存储器块被访问，当输出有效数据时，这样的有效数据输出由数据有效信号发出。

69. 发明授权

US5835448A Clock synchronous semiconductor memory device for determining an operation mode 失效
标题翻译：用于确定操作模式的时钟同步半导体存储器件
公开(公告)号：US5835448A
公开(公告)日：1998-11-10
申请号：US880153
申请日：1997-06-20
申请人： Jun Ohtani , Akira Yamazaki , Katsumi Dosaka
发明人： Jun Ohtani , Akira Yamazaki , Katsumi Dosaka
IPC分类号： G11C11/41 , G06F12/08 , G11C7/10 , G11C7/22 , G11C11/00 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/409 , G11C11/4096 , G11C8/00
CPC分类号： G11C7/1072 , G11C11/005 , G11C11/4076 , G11C11/4096 , G11C7/103 , G11C7/1051 , G11C7/22
摘要： A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.
摘要翻译：当外部时钟信号Ka处于非活动状态时，信号输入缓冲器达到通过状态，并且响应于外部信号产生内部信号，并且当外部时钟信号处于非活动状态时，信号输入缓冲器达到锁存状态。响应于正在使用的从属数据寄存器的检测，执行从通过从属数据寄存器将数据存储在DRAM阵列中的主数据寄存器的数据传送。从数据寄存器存储要传输到SRAM阵列的数据或要外部访问的数据。因此，提供了可高速访问并且不等待的同步半导体存储器件。此外，响应于外部时钟信号的激活，内部时钟信号被激活预定时间以确保精确的内部操作定时。

70. 发明授权

US5774409A Multi-bank dRAM suitable for integration with processor on common semiconductor chip 失效
标题翻译：多组dRAM适合与公共半导体芯片上的处理器集成
公开(公告)号：US5774409A
公开(公告)日：1998-06-30
申请号：US797081
申请日：1997-02-10
申请人： Akira Yamazaki , Katsumi Dosaka
发明人： Akira Yamazaki , Katsumi Dosaka
IPC分类号： G06F12/08 , G06F12/00 , G06F12/02 , G06F12/06 , G11C8/12 , G11C11/401 , G11C11/406 , G11C11/407 , G11C11/408 , G11C11/409
CPC分类号： G11C8/12 , G06F12/0215 , G06F12/0893 , Y02B60/1225
摘要： A dynamic random access memory DRAM includes banks which are driven to active or inactive states independently of each other. Activation/inactivation of these banks are controlled by row controllers operating independently of each other, whereby a page or word line can be selected in each of the banks, a page hit rate can be increased, and the number of array precharge operation times in a page error as well as power consumption can be reduced in response. Thus, the cache hit rate of a processor having a built-in DRAM is increased and power consumption is reduced.
摘要翻译：动态随机存取存储器DRAM包括彼此独立地被驱动到活动或非活动状态的存储体。这些组的激活/失活由彼此独立地操作的行控制器控制，从而可以在每个存储体中选择页面或字线，可以增加页面命中率，并且在一个或多个存储器中的阵列预充电操作次数可以减少页面错误以及功耗。因此，具有内置DRAM的处理器的高速缓存命中率增加并且功耗降低。

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