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61. 发明授权

US07768867B2 Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：US07768867B2
公开(公告)日：2010-08-03
申请号：US11761470
申请日：2007-06-12
申请人： Yoji Nishio , Yutaka Uematsu , Seiji Funaba , Hideki Osaka , Tsutomu Hara , Koichiro Aoki
发明人： Yoji Nishio , Yutaka Uematsu , Seiji Funaba , Hideki Osaka , Tsutomu Hara , Koichiro Aoki
IPC分类号： G11C8/00
CPC分类号： G11C7/02 , G11C5/02 , G11C5/04 , H01L25/105 , H01L2924/0002 , H01L2924/15311 , H01L2924/15331 , H01L2924/00
摘要： Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.
摘要翻译：叠层半导体器件包括多个存储器芯片，堆叠在一起，其中高速传输中的波形失真被去除。堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。数据选通信号和反相数据选通信号相互配合。用于数据选通信号L4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于/ DQS信号L5的反相数据选通信号线连接到第二存储芯片11的反相数据选通信号（/ DQS）焊盘存储芯片12。

62. 发明申请

US20090245424A1 SEMICONDUCTOR DEVICE, MEMORY DEVICE AND MEMORY MODULE HAVING DIGITAL INTERFACE 有权
标题翻译：半导体器件，存储器件和具有数字接口的存储器模块
公开(公告)号：US20090245424A1
公开(公告)日：2009-10-01
申请号：US12481798
申请日：2009-06-10
申请人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
发明人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
IPC分类号： H03K9/00
CPC分类号： H03K5/082 , H03K5/135
摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.
摘要翻译：本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收机接收到的数据的状态，并根据保持的状态和输入来调整提取输入数据的定时数据。作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

63. 发明授权

US07558336B2 Semiconductor device, memory device and memory module having digital interface 失效
标题翻译：半导体器件，存储器件和具有数字接口的存储器模块
公开(公告)号：US07558336B2
公开(公告)日：2009-07-07
申请号：US10982946
申请日：2004-11-08
申请人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
发明人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
IPC分类号： H03K9/00 , H04B3/46 , G06K5/04 , H03M13/00 , G06F13/42
CPC分类号： H03K5/082 , H03K5/135
摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.
摘要翻译：本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收器接收到的数据的状态，并且根据保持的状态和输入来调整提取输入数据的定时数据。作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

64. 发明授权

US07515157B2 Data transmission device, data transfer system and method 失效
标题翻译：数据传输装置，数据传输系统及方法
公开(公告)号：US07515157B2
公开(公告)日：2009-04-07
申请号：US10333132
申请日：2000-12-14
申请人： Toyohiko Komatsu , Hideki Osaka , Masashi Horiguchi , Susumu Hatano , Kazuya Ito
发明人： Toyohiko Komatsu , Hideki Osaka , Masashi Horiguchi , Susumu Hatano , Kazuya Ito
IPC分类号： G06F13/14
CPC分类号： H04L12/40
摘要： A data transfer method is executed to transit a three-state transmitting circuit from a high-impedance state into a data output state, transmit a preamble (dummy data) onto a bus, and sequentially transmit the essential data. The shortening of a waveform caused in the first data piece after the transition from the high-impedance state into the data output state is executed against the preamble and no shortening of a waveform is not brought about in the essential data subsequent to the preamble. This makes it possible to exclude the limitation on speeding up the data transfer imposed by the shortening of the waveform.
摘要翻译：执行数据传送方法以将三状态发送电路从高阻抗状态转移到数据输出状态，将前导码（虚拟数据）发送到总线上，并且顺序发送基本数据。在从高阻抗状态转换到数据输出状态之后，在第一数据段中引起的波形的缩短针对前同步码执行，并且在前导码之后的基本数据中不会引起波形的缩短。这使得可以排除由于缩短波形而加速数据传输的限制。

65. 发明授权

US07505285B2 Main board for backplane buses 失效
标题翻译：背板总线主板
公开(公告)号：US07505285B2
公开(公告)日：2009-03-17
申请号：US11404912
申请日：2006-04-17
申请人： Hideki Osaka
发明人： Hideki Osaka
IPC分类号： H01R12/16
CPC分类号： H05K1/0236 , H05K1/0237 , H05K1/0298 , H05K1/167 , H05K2201/044 , H05K2201/09681 , H05K2201/0969
摘要： A motherboard for backplane buses is provided that reduces noise due to entry of external signals into signal wiring which interconnects modules, or noise due to any external signals entering a power supply after being routed around the power supply.An EBG pattern formed up of two wiring regions different from each other in impedance is periodically disposed in at least three arrays as part of the power supply layer(s) constituting a microstripline structure (one layer adjacent to a signal layer is a power supply layer, and the other layer is interposed in air) or a stripline structure (both layers adjacent to a signal layer are power supply layers); the part of the power supply layer(s) not being involved in signal transmission between the modules on the motherboard for backplane buses.
摘要翻译：提供了用于背板总线的主板，其将由于外部信号进入到互连模块的信号布线而引起的噪声，或者由于任何外部信号在绕过电源而进入电源之后产生的噪声。由构成微带结构的电源层的一部分（至少与信号层相邻的一层是供电层），在至少三个阵列中周期性地设置由阻抗彼此不同的两个布线区域形成的EBG图案，另一层插入空气）或带状线结构（与信号层相邻的两层是电源层）; 电源层的一部分不涉及用于背板总线的主板上的模块之间的信号传输。

66. 发明申请

US20080290495A1 Low noise semiconductor device 有权
标题翻译：低噪声半导体器件
公开(公告)号：US20080290495A1
公开(公告)日：2008-11-27
申请号：US12068606
申请日：2008-02-08
申请人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
发明人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
IPC分类号： H01L23/528
CPC分类号： H05K1/0231 , H01L23/50 , H01L23/5385 , H01L23/66 , H01L2224/16225 , H01L2924/12044 , H01L2924/3011 , H05K1/09 , H05K1/111 , H05K1/167 , H05K2201/0352 , H05K2201/0391 , H05K2201/09236 , H05K2201/09309 , H05K2201/09481 , H05K2201/09781 , H05K2201/10636 , H05K2201/10674 , Y02P70/611 , H01L2924/00
摘要： As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.
摘要翻译：作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持阻抗低在低频。

67. 发明授权

US07447708B2 Data processing apparatus and network system that outputs quality of service information to a user 失效
标题翻译：向用户输出服务质量信息的数据处理装置和网络系统
公开(公告)号：US07447708B2
公开(公告)日：2008-11-04
申请号：US11054387
申请日：2005-02-10
申请人： Ryuichi Hattori , Toshihiko Ogura , Takashi Oeda , Koichi Okazawa , Hideki Osaka , Tsunehiro Tobita , Tsutomu Hara
发明人： Ryuichi Hattori , Toshihiko Ogura , Takashi Oeda , Koichi Okazawa , Hideki Osaka , Tsunehiro Tobita , Tsutomu Hara
IPC分类号： G06F17/30 , G06F15/16
CPC分类号： G06F9/5055 , G06F9/5044 , G06F2209/5015 , H04L29/12047 , H04L41/5009 , H04L61/15 , H04L67/36
摘要： In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.
摘要翻译：在通过网络彼此连接的每个信息处理设备中，布置了其功能和性能被注册到其中的服务质量（QOS）表。当信息处理设备另外与网络链接时，其QOS表被自动地注册到网络的本地目录，使得代理将QOS表的内容转换成要经由用户界面提供给用户的服务信息。由于操作，连接到网络的每个信息处理设备的功能和性能的信息被转换成用户的服务信息。因此，用户可以更多地直接接收必要的服务。

68. 发明申请

US20080266031A1 SEMICONDUCTOR DEVICE AND WIRING PART THEREOF 有权
标题翻译：半导体器件及其接线部分
公开(公告)号：US20080266031A1
公开(公告)日：2008-10-30
申请号：US12060941
申请日：2008-04-02
申请人： Yutaka UEMATSU , Hideki Osaka , Yoji Nishio , Eiichi Suzuki
发明人： Yutaka UEMATSU , Hideki Osaka , Yoji Nishio , Eiichi Suzuki
IPC分类号： H01P1/00
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H05K1/0231 , H05K1/111 , H05K2201/0175 , H05K2201/0179 , H05K2201/09763 , H05K2201/10515 , H05K2201/10522 , H05K2201/10734 , H01L2924/00
摘要： A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 μm therebetween.
摘要翻译：提供了能够实现半导体器件的安装密度和噪声降低的改进的技术。安装在印刷电路板上的LSI包括接地BGA球和电源BGA球，以从印刷线路板获得电源，并且接地BGA球和电源BGA球彼此靠近地布置。去耦电容器安装在印刷电路板上，并具有第一端子和第二端子。接地BGA球和第一端子通过第一金属电极板连接，电力BGA球和第二端子通过第二金属电极板连接。第一金属电极板和第二金属电极板在其间插入厚度等于或小于1μm的电介质膜。

69. 发明授权

US07187069B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07187069B2
公开(公告)日：2007-03-06
申请号：US10981676
申请日：2004-11-05
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H01L23/02 , H01L23/34
CPC分类号： H01L23/642 , H01L23/5223 , H01L23/5228 , H01L23/5286 , H01L23/647 , H01L25/105 , H01L2224/73204 , H01L2924/19105 , H01L2924/3011
摘要： The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.
摘要翻译：本发明提供一种技术，其不会引起两个问题，即（1）增加电源/接地引脚的数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变为布线并引入输出缓冲区。更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

70. 发明申请

US20070047354A1 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：US20070047354A1
公开(公告)日：2007-03-01
申请号：US11511262
申请日：2006-08-29
申请人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
发明人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
IPC分类号： G11C7/02
CPC分类号： G11C5/147 , G11C5/02 , G11C7/02 , H01L24/48 , H01L2224/05554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48227 , H01L2224/4847 , H01L2924/00014 , H01L2924/10161 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor module comprises a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device comprises a first electrode. The second semiconductor device comprises a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.
摘要翻译：半导体模块包括第一半导体器件，第二半导体器件和参考电压提供电路。第一半导体器件包括第一电极。第二半导体器件包括第二电极。参考电压提供电路用于向第一电极和第二电极提供参考电位，并用于抑制在第一电极和第二电极之间传递的噪声。

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