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    • 61. 发明授权
    • Well treating methods and devices using particulate blends
    • 使用颗粒混合物的良好处理方法和装置
    • US5492178A
    • 1996-02-20
    • US323175
    • 1994-12-15
    • Philip D. NguyenJoe R. MurpheyDavid L. Brown
    • Philip D. NguyenJoe R. MurpheyDavid L. Brown
    • C09K8/62C09K8/80E21B43/02E21B43/267A01D43/04
    • E21B43/267C09K8/62C09K8/80E21B43/025
    • Fracturing, frac-pack, and gravel packing procedures are provided which utilize a treating composition comprising a carrier fluid and a particulate blend. The particulate blend consists essentially of a large particulate material and a small particulate material. The large particulate material consists essentially of particles smaller than about 4 mesh but not smaller than about 40 mesh. The small particulate material consists essentially of particles smaller than about 16 mesh but not smaller than about 100 mesh. The small particulate material is present in the particulate blend in an amount in the range of from about 5% to about 60% by weight based on the amount of the large particulate material present in the particulate blend. A prepacked screening device including a large particulate/small particulate blend of the type just described is also provided.
    • 提供了利用包含载体流体和颗粒混合物的处理组合物的压裂,压裂包装和砾石填充程序。 颗粒混合物基本上由大颗粒材料和小颗粒材料组成。 大颗粒材料基本上由小于约4目但不小于约40目的颗粒组成。 小颗粒材料基本上由小于约16目但不小于约100目的颗粒组成。 基于颗粒混合物中存在的大颗粒材料的量,小颗粒材料以约5重量%至约60重量%的量存在于颗粒混合物中。 还提供了包括刚刚描述的类型的大颗粒/小颗粒混合物的预包装筛选装置。
    • 64. 发明授权
    • Multi-mode digital phase lock loop
    • 多模数字锁相环
    • US5436937A
    • 1995-07-25
    • US11926
    • 1993-02-01
    • David L. BrownPaul D. Marko
    • David L. BrownPaul D. Marko
    • H03L7/08H03L7/099H04L7/033H03D3/24
    • H03L7/0992H03L7/08H04L7/0331
    • A multi-mode PLL circuit (100) includes an early/late bit transition accumulator (108) for accumulating the number of incoming bit transitions which are early or late. This allows for PLL (100) to provide adjustments based on a predetermined number of accumulated early/late accumulations or based on an average of early/late transitions over a predetermined period of time. PLL (100) further includes a frequency offset circuit (200) which includes a frequency error accumulator which is used to maintain a frequency offset history and to control the loop frequency. This allows for very narrow band operation of the first order digital PLL while maintaining stable operation.
    • 多模式PLL电路(100)包括用于累加早期或晚期的输入位转换次数的早/晚位转换累加器(108)。 这允许PLL(100)基于预定数量的累加的早/晚累积或者基于在预定时间段内的早/晚转换的平均值来提供调整。 PLL(100)还包括频率偏移电路(200),其包括用于维持频率偏移历史并控制环路频率的频率误差累加器。 这允许一阶数字PLL的非常窄的频带操作,同时保持稳定的操作。