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61. 发明申请

US20060179241A1 Data processing system and method for predictively selecting a scope of broadcast of an operation 有权
标题翻译：用于预测性地选择操作的广播范围的数据处理系统和方法
公开(公告)号：US20060179241A1
公开(公告)日：2006-08-10
申请号：US11054886
申请日：2005-02-10
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke
IPC分类号： G06F13/28
CPC分类号： G06F12/0844 , G06F12/0817 , G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains coupled for communication. The first and second coherency domains each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains based, at least in part, upon a type of the operation. The master then performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.
摘要翻译：高速缓存一致数据处理系统至少包括耦合用于通信的第一和第二相干域。第一和第二相关域各自包括第一和第二高速缓存存储器中的相应一个。第一相关域中的主机至少部分地基于类型，从包括第一相关域的第一范围和包括第一和第二相干域两者的第二范围中选择操作的初始广播的范围的操作。然后，主机使用所选择的范围在高速缓存相干数据处理系统内执行操作的初始广播。

62. 发明申请

US20060179223A1 L2 cache array topology for large cache with different latency domains 有权
标题翻译：具有不同延迟域的大型缓存的L2缓存阵列拓扑
公开(公告)号：US20060179223A1
公开(公告)日：2006-08-10
申请号：US11054930
申请日：2005-02-10
申请人： Leo Clark , Guy Guthrie , Kirk Livingston , William Starke
发明人： Leo Clark , Guy Guthrie , Kirk Livingston , William Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0822 , G06F12/0824
摘要： A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency. One set of wires oriented along a horizontal direction may be used to output the cache line, while another set of wires oriented along a vertical direction may be used for maintenance of the cache sectors. A given cache line is further preferably spread across sectors in different rows or cache ways. For example, a cache line can be 128 bytes and spread across four sectors in four different columns, each sector containing 32 bytes of the cache line, and the cache line is output over four successive clock cycles with one sector being transmitted during each of the four cycles.
摘要翻译：缓存存储器逻辑地将高速缓存行与高速缓存阵列的至少两个缓存扇区相关联，其中不同扇区具有不同的输出延迟，并且对于负载命中，基于它们的等待时间来选择性地启用高速缓存扇区以在连续的时钟周期上输出高速缓存行。优选使用具有较高传输速度的较大导线来输出与所请求的存储块相对应的高速缓存行。在说明性实施例中，高速缓存器配置有高速缓存扇区的行和列，并且给定的高速缓存行分布在不同列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一等待时间的第一列中并且所述给定高速缓存行的另一部分位于具有大于所述第一等待时间的第二等待时间的第二列中。可以使用沿水平方向定向的一组线来输出高速缓存线，而沿着垂直方向定向的另一组线可以用于高速缓存扇区的维护。给定的高速缓存行进一步优选地分布在不同行或高速缓存方式的扇区之间。例如，高速缓存行可以是128字节并且分布在四个不同列中的四个扇区上，每个扇区包含32个字节的高速缓存行，并且高速缓存行在四个连续的时钟周期内被输出，在每个四个周期。

63. 发明申请

US20070168639A1 Data processing system and method for selecting a scope of broadcast of an operation by reference to a translation table 审中-公开
标题翻译：参考翻译表选择操作的广播范围的数据处理系统和方法
公开(公告)号：US20070168639A1
公开(公告)日：2007-07-19
申请号：US11333607
申请日：2006-01-17
申请人： John McCalpin , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： John McCalpin , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0833 , G06F12/10 , G06F2212/507
摘要： A data processing system includes at least first and second coherency domains coupled by an interconnect fabric. A memory coupled to the interconnect fabric includes an address translation table having a translation table entry utilized to translate virtual memory addresses to real memory addresses. The translation table entry also includes scope information for broadcast operations targeting addresses within a memory region associated with the translation table entry. Scope prediction logic within the first coherency domain predictively selects a scope of broadcast of an operation on an interconnect fabric of the data processing system by reference to the scope information within the address translation table entry.
摘要翻译：数据处理系统至少包括由互连结构耦合的第一和第二相干域。耦合到互连结构的存储器包括具有用于将虚拟存储器地址转换为实际存储器地址的转换表项的地址转换表。转换表条目还包括针对与转换表条目相关联的存储器区域内的地址的广播操作的范围信息。第一相干域内的范围预测逻辑通过参考地址转换表条目中的范围信息预测性地选择数据处理系统的互连结构上的操作的广播范围。

64. 发明申请

US20060179252A1 Data processing system and method for efficient communication utilizing an In coherency state 有权
标题翻译：数据处理系统和利用一致性状态的高效通信方法
公开(公告)号：US20060179252A1
公开(公告)日：2006-08-10
申请号：US11055305
申请日：2005-02-10
申请人： Jason Cantin , James Fields , Steven Kunkel , William Starke
发明人： Jason Cantin , James Fields , Steven Kunkel , William Starke
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。第一相关域包括第一高速缓冲存储器，并且第二相干域包括相干第二高速缓冲存储器。数据处理系统的第一相干域内的第一高速缓冲存储器在与地址标签和一致性状态字段相关联的存储位置中保存存储器块。相关性状态字段被设置为指示地址标签有效的状态，存储位置不包含有效数据，并且该存储器块可能仅在第一相干域内被缓存。

65. 发明申请

US20060184836A1 Method, apparatus, and computer program product in a processor for dynamically during runtime allocating memory for in-memory hardware tracing 失效
标题翻译：处理器中的方法，装置和计算机程序产品在运行时动态地分配用于存储器内硬件跟踪的存储器
公开(公告)号：US20060184836A1
公开(公告)日：2006-08-17
申请号：US11055977
申请日：2005-02-11
申请人： Ra'ed Al-Omari , Alexander Mericas , William Starke
发明人： Ra'ed Al-Omari , Alexander Mericas , William Starke
IPC分类号： G06F11/00
CPC分类号： G06F11/2268 , G06F11/3476 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.
摘要翻译：在处理器中公开了一种方法，装置和计算机程序产品，用于在运行时期间动态地为存储器内硬件跟踪分配存储器。处理器包含在数据处理系统中。处理器包括使用系统总线耦合在一起的多个处理单元。处理单元包括控制系统存储器的存储器控制器。确定存储跟踪数据所需的特定大小的系统存储器。硬件跟踪设施在数据处理系统完成启动之后动态地请求要分配给硬件跟踪设备的系统内存的特定大小，用于存储由硬件跟踪设备捕获的跟踪数据。固件选择系统内存中的特定位置。所有特定位置在一起是特定的尺寸。固件分配由硬件跟踪设备专门使用的特定位置。

66. 发明申请

US20060179238A1 Store stream prefetching in a microprocessor 失效
标题翻译：在微处理器中存储流预取
公开(公告)号：US20060179238A1
公开(公告)日：2006-08-10
申请号：US11054871
申请日：2005-02-10
申请人： John Griswell , Hung Le , Francis O'Connell , William Starke , Jeffrey Stuecheli , Albert Williams
发明人： John Griswell , Hung Le , Francis O'Connell , William Starke , Jeffrey Stuecheli , Albert Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/30047 , G06F9/383 , G06F12/0811
摘要： In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.
摘要翻译：在具有加载/存储单元和预取硬件的微处理器中，预取硬件包括预取队列，其包含指示分配的数据流的条目。预取引擎接收与由加载/存储单元执行的存储指令相关联的地址。预取引擎通过将队列中的条目与包含多个高速缓存块的地址的窗口进行比较来确定是否对与存储指令相对应的预取队列中的条目进行分配，其中地址窗口从接收到的地址导出。预取引擎将预取队列中的条目与两个连续高速缓存块的窗口进行比较。当预取队列中的任何条目都在地址窗口内时，预取引擎抑制新条目的分配。当存储指令的数据地址等于地址窗口的边界区域中的地址时，预取引擎进一步抑制新条目的分配。

67. 发明申请

US20070266126A1 DATA PROCESSING SYSTEM AND METHOD OF DATA PROCESSING SUPPORTING TICKET-BASED OPERATION TRACKING 审中-公开
标题翻译：数据处理系统和数据处理方法支持基于票单的操作跟踪
公开(公告)号：US20070266126A1
公开(公告)日：2007-11-15
申请号：US11279643
申请日：2006-04-13
申请人： Leo Clark , James Fields , Benjiman Goodman , William Starke , Jeffrey Stuecheli
发明人： Leo Clark , James Fields , Benjiman Goodman , William Starke , Jeffrey Stuecheli
IPC分类号： G06F15/173
CPC分类号： G06F12/0831 , G06F12/0897 , G06F12/1458
摘要： A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.
摘要翻译：数据处理系统包括由多个通信链路耦合用于点对点通信的多个处理单元，使得多个处理单元中的多个不同处理单元之间的通信中的至少一些通过多个处理单元之间的中间处理单元发送处理单位。该通信包括具有请求的操作和表示对请求的系统响应的组合响应。至少每个中间处理单元包括启动第一操作的一个或多个主机，至少接收由所述多个处理单元中的至少另一个处理单元发起的至少第二操作的侦听器;存储由所述多个处理单元发起的第一操作的主标签的物理队列在该处理单元内的一个或多个主设备，以及票据机构，其分配在中间处理单元处观察到的第二操作，该票单号指示关于由中间处理单元观察到的其他第二操作的观察次序。票务机制将分配给操作员的操作的票号提供给操作的组合响应进行处理。

68. 发明申请

US20070073998A1 Data processing system, method and interconnect fabric supporting high bandwidth communication between nodes 失效
标题翻译：支持节点之间高带宽通信的数据处理系统，方法和互连结构
公开(公告)号：US20070073998A1
公开(公告)日：2007-03-29
申请号：US11236458
申请日：2005-09-27
申请人： Vicente Chung , Benjiman Goodman , Praveen Reddy , William Starke
发明人： Vicente Chung , Benjiman Goodman , Praveen Reddy , William Starke
IPC分类号： G06F15/00
CPC分类号： G06F15/17337
摘要： A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. Each of the plurality of first processing units is coupled to a respective one of the plurality of second processing units in the second processing node by a respective one of a plurality of point-to-point links.
摘要翻译：数据处理系统包括第一处理节点和第二处理节点。第一处理节点包括彼此耦合以进行通信的多个第一处理单元，并且第二处理节点包括彼此耦合以进行通信的多个第二处理单元。多个第一处理单元中的每一个通过多个点对点链接中的相应一个耦合到第二处理节点中的多个第二处理单元中的相应一个。

69. 发明申请

US20060184834A1 Method, apparatus, and computer program product in a processor for concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers 失效
标题翻译：处理器中的方法，装置和计算机程序产品，用于在跟踪过程和使用可编程可变数量的共享存储器写入缓冲器的非跟踪处理之间并发共享存储器控制器
公开(公告)号：US20060184834A1
公开(公告)日：2006-08-17
申请号：US11055845
申请日：2005-02-11
申请人： Ra'ed Al-Omari , Alexander Mericas , William Starke
发明人： Ra'ed Al-Omari , Alexander Mericas , William Starke
IPC分类号： G06F11/00
CPC分类号： G06F11/2268 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.
摘要翻译：公开了一种方法，装置和计算机程序产品，用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。硬件跟踪设备捕获处理器中的硬件跟踪数据。硬件跟踪工具包含在处理器内。使用系统总线将硬件跟踪数据传输到系统存储器。系统内存包含在系统中。当将硬件跟踪数据发送到系统总线时，系统总线能够被包括在处理节点中的处理单元利用。系统内存的一部分用于存储跟踪数据。系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问，同时系统存储器的一部分用于存储跟踪数据。

70. 发明申请

US20060184833A1 Method, apparatus, and computer program product in a processor for performing in-memory tracing using existing communication paths 失效
标题翻译：处理器中的方法，装置和计算机程序产品，用于使用现有通信路径执行内存中跟踪
公开(公告)号：US20060184833A1
公开(公告)日：2006-08-17
申请号：US11055821
申请日：2005-02-11
申请人： Ra'ed Al-Omari , Alexander Mericas , William Starke
发明人： Ra'ed Al-Omari , Alexander Mericas , William Starke
IPC分类号： G06F11/00
CPC分类号： G06F11/2268 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.
摘要翻译：公开了一种用于使用现有系统总线在处理器中执行存储器内硬件跟踪的方法，装置和计算机程序产品。处理器包括利用系统总线耦合在一起的多个处理单元。处理单元包括控制系统存储器的存储器控制器。利用系统总线在处理单元之间传送信息。信息根据标准系统总线协议进行格式化。使用直接耦合到系统总线的硬件跟踪功能来捕获硬件跟踪数据。系统总线用于将硬件跟踪数据发送到存储器控制器以存储在系统存储器中。存储器控制器直接耦合到系统总线。硬件跟踪数据根据标准系统总线协议进行格式化，以便通过系统总线进行传输。

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