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61. 发明授权

US6061755A Method of layering cache and architectural specific functions to promote operation symmetry 失效
标题翻译：分层缓存和架构特定功能的方法，以促进操作对称
公开(公告)号：US6061755A
公开(公告)日：2000-05-09
申请号：US839441
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
IPC分类号： G06F12/08 , G06F13/38 , G06F12/00
CPC分类号： G06F12/0831
摘要： Cache and architectural functions within a cache controller are layered so that architectural operations may be symmetrically treated regardless of whether initiated by a local processor or by a horizontal processor. The same cache controller logic which handles architectural operations initiated by a horizontal device also handles architectural operations initiated by a local processor. Architectural operations initiated by a local processor are passed to the system bus and self-snooped by the controller. If necessary, the architectural controller changes the operation protocol to conform to the system bus architecture.
摘要翻译：高速缓存控制器内的缓存和架构功能被分层，使得架构操作可以被对称地处理，而不管是由本地处理器还是由水平处理器启动。处理由水平设备发起的架构操作的相同缓存控制器逻辑也处理由本地处理器启动的架构操作。由本地处理器启动的架构操作被传递给系统总线，并由控制器自行侦测。如果需要，架构控制器改变操作协议以符合系统总线体系结构。

62. 发明授权

US5951668A Method and system for transferring data between buses having differing ordering policies 失效
公开(公告)号：US5951668A
公开(公告)日：1999-09-14
申请号：US934407
申请日：1997-09-19
申请人： Ravi Kumar Arimilli , Derek Edward Williams
发明人： Ravi Kumar Arimilli , Derek Edward Williams
IPC分类号： G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4013 , G06F13/36
摘要： A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering policy, and for transferring the ordered data on a second bus having the second ordering policy. The system includes a plurality of execution units for storing operations and executing the transfer of data between the first and second buses. Each one of the execution units are assigned to a group which represent a class of operations. The apparatus further includes intra prioritizing means, for each group, for prioritizing the stored operations according to the second ordering policy exclusive of the operation stored in the other group. The system also includes inter prioritizing means for determining which one of the prioritized operations can proceed to execute according to the second ordering policy.

63. 发明授权

US5935234A Method and system for controlling access to a shared resource in a data processing system utilizing pseudo-random priorities 失效
标题翻译：用于利用伪随机优先级来控制对数据处理系统中的共享资源的访问的方法和系统
公开(公告)号：US5935234A
公开(公告)日：1999-08-10
申请号：US839436
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
IPC分类号： G06F15/16 , G06F13/364 , G06F15/177 , G06F13/14
CPC分类号： G06F13/364
摘要： A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is assigned a current priority, at least the highest current priority being determined substantially randomly with respect to previous priorities of the requestors. In response to the current priorities of the requestors, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.
摘要翻译：描述了用于控制对数据处理系统中的共享资源的访问的方法和系统。根据该方法，通过共享资源的多个请求者生成对资源的访问的多个请求。每个请求者被分配当前优先级，至少最高当前优先级相对于请求者的先前优先级基本随机地确定。响应请求者的当前优先级，授予访问该资源的请求。在一个实施例中，与被许可的请求相对应的请求者用信号通知其请求已经被许可，并且与被拒绝的请求相对应的请求者用信号通知其请求未被授予。

64. 发明授权

US5909561A Apparatus and method for separately layering cache and architectural specific functions in different operational controllers to facilitate design extension 失效
标题翻译：用于在不同的操作控制器中单独分层缓存和架构特定功能以便于设计扩展的装置和方法
公开(公告)号：US5909561A
公开(公告)日：1999-06-01
申请号：US839443
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0888
摘要： Cache and architectural functions within a cache controller are layered and provided with generic interfaces, isolating controller logic from specific architectural complexities. Controller logic may thus be readily duplicated to extend a nonshared cache controller design to a shared cache controller design, with only straightforward modifications required. Throttling of processor-initiated operations handled by the same controller logic resolves operation flow rate issues with acceptable performance trade-offs.
摘要翻译：高速缓存控制器中的缓存和架构功能分层并提供通用接口，将控制器逻辑与特定架构复杂性隔离开来。因此，控制器逻辑可以容易地重复，以将非共享高速缓存控制器设计扩展到共享高速缓存控制器设计，只需要直接的修改。由同一控制器逻辑处理的由处理器启动的操作的调节可以解决具有可接受的性能权衡的操作流速问题。

65. 发明授权

US08296740B2 Annotating system traces with control program information and presenting annotated system traces 失效
标题翻译：用控制程序信息注释系统跟踪，并显示注释的系统跟踪
公开(公告)号：US08296740B2
公开(公告)日：2012-10-23
申请号：US12057829
申请日：2008-03-28
申请人： Wolfgang Roesner , Derek Edward Williams
发明人： Wolfgang Roesner , Derek Edward Williams
IPC分类号： G06F9/44
CPC分类号： G06F11/3664 , G06F11/3636
摘要： The signal state that a signal of interest within a system under test has during each of a plurality of cycles of operation of the system under test is stored in a trace file. In association with the signal state, information regarding a requested access to the signal state by a control program during a particular cycle among the plurality of cycles is also stored. From the trace files a presentation is generated that presents, for at least a signal of interest within the system under test, a plurality of signal state indications, each indicating a respective state that the signal had during a one of a plurality of cycles of operation of the system under test. The presentation also indicates, in a graphically distinctive manner, at least one cycle of operation during which a control program requested access to a state of the signal, so that the influence of the control program on the state of the system under test is visually apparent.
摘要翻译：被测系统中感兴趣的信号在被测系统的多个操作周期中的每一个期间的信号状态被存储在跟踪文件中。与信号状态相关联，还存储关于在多个周期中的特定周期期间由控制程序请求的访问信号状态的信息。从跟踪文件中产生一个演示文稿，对于至少在被测系统内感兴趣的信号，呈现多个信号状态指示，每个信号状态指示各自表示信号在多个操作周期之一中具有的状态的被测系统。演示文稿还以图形上独特的方式指示至少一个操作周期，在该周期期间控制程序请求访问信号的状态，使得控制程序对被测系统的状态的影响在视觉上是明显的。

66. 发明授权

US07921389B2 Controlling operation of a digital system utilizing register entities 有权
标题翻译：使用注册实体控制数字系统的操作
公开(公告)号：US07921389B2
公开(公告)日：2011-04-05
申请号：US12146208
申请日：2008-06-25
申请人： Wolfgang Roesner , Derek Edward Williams
发明人： Wolfgang Roesner , Derek Edward Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/505
摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.
摘要翻译：在至少一个硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的至少一个设计实体。设计实体逻辑地包含第一和第二锁存器，每个锁存器具有相应的多个不同的可能锁存值。利用一个或多个语句，第一拨号实例与第一锁存器相关联，并且第二拨号实例与第二锁存器相关联。因此，第一拨号实例的设置控制多个不同可能值中的哪一个加载到第一锁存器中，并且第二拨号实例的设置控制多个不同可能值中的哪一个加载到第二锁存器中。通过语句，寄存器实例同时与第一和第二锁存器相关联，使得寄存器实例的设置控制加载在第一和第二锁存器中的锁存值。

67. 发明授权

US07895558B2 Configuration specification language supporting arbitrary mapping functions for configuration constructs 有权
标题翻译：配置规范语言支持配置结构的任意映射功能
公开(公告)号：US07895558B2
公开(公告)日：2011-02-22
申请号：US12110047
申请日：2008-04-25
申请人： Wolfgang Roesner , Derek Edward Williams
发明人： Wolfgang Roesner , Derek Edward Williams
IPC分类号： G06F17/50 , G06F19/00 , G06F9/00 , G06F15/177 , G06F1/24 , G06F9/44
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial.
摘要翻译：公开了一种将映射函数与由一个或多个硬件描述语言（HDL）文件定义的数字设计的配置结构相关联的方法。根据该方法，在HDL文件中，在形成数字设计的至少一部分的设计实体内指定配置锁存器。此外，指定了一个Dial，其定义了多个输入值中的每一个与多个不同输出值中的相应的一个之间的关系。 HDL文件还包括一个语句，用于与配置锁存器相关联地实例化Dial的实例，使得在配置锁存器中包含的值与Dial的实例的输入值之间存在一一对应的对应关系。 HDL文件还包括将Dial与将映射功能相关联的语句，该映射函数将选择的变换应用于从Dial的实例读取或写入的值。

68. 发明授权

US07818364B2 Method and data processing system for microprocessor communication in a cluster-based multi-processor system 失效
标题翻译：基于群集的多处理器系统中微处理器通信的方法和数据处理系统
公开(公告)号：US07818364B2
公开(公告)日：2010-10-19
申请号：US11952479
申请日：2007-12-07
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/76 , G06F15/163
CPC分类号： H04L69/16 , G06F15/17 , H04L12/42 , H04L67/1002 , H04L69/161 , H04W28/14
摘要： A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存行，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

69. 发明授权

US07454737B2 Method, system and program product for specifying and using register entities to configure a simulated or physical digital system 失效
标题翻译：用于指定和使用寄存器实体配置模拟或物理数字系统的方法，系统和程序产品
公开(公告)号：US07454737B2
公开(公告)日：2008-11-18
申请号：US11552306
申请日：2006-10-24
申请人： Wolfgang Roesner , Derek Edward Williams
发明人： Wolfgang Roesner , Derek Edward Williams
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5022 , G06F17/505
摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.
摘要翻译：在至少一个硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的至少一个设计实体。设计实体逻辑地包含第一和第二锁存器，每个锁存器具有相应的多个不同的可能锁存值。利用一个或多个语句，第一拨号实例与第一锁存器相关联，并且第二拨号实例与第二锁存器相关联。因此，第一拨号实例的设置控制多个不同可能值中的哪一个加载到第一锁存器中，并且第二拨号实例的设置控制多个不同可能值中的哪一个加载到第二锁存器中。通过语句，寄存器实例同时与第一和第二锁存器相关联，使得寄存器实例的设置控制加载在第一和第二锁存器中的锁存值。

70. 发明申请

US20080249758A1 PROGRAM PRODUCT FOR DEFINING AND RECORDING MINIMUM AND MAXIMUM EVENT COUNTS OF A SIMULATION UTILIZING A HIGH LEVEL LANGUAGE 失效
标题翻译：用于定义和记录使用高级语言的模拟的最小和最大事件计数的程序产品
公开(公告)号：US20080249758A1
公开(公告)日：2008-10-09
申请号：US12106416
申请日：2008-04-21
申请人： Carol Ivash Gabele , Wolfgang Roesner , Derek Edward Williams
发明人： Carol Ivash Gabele , Wolfgang Roesner , Derek Edward Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation model, occurrences of the outlying count event are counted to obtain a count event value. Simulation result data obtained from simulating the design is then received and processed. In the processing, the count event value is recorded within a data storage subsystem responsive to a determination of whether or not the count event value of the outlying count event exceeds a previously recorded count event value.
摘要翻译：根据模拟处理的一种方法，诸如运行时执行程序（rtx）的仪器代码接收描述计数事件的一个或多个语句，并将计数事件识别为外部计数事件。在使用HDL仿真模型模拟设计的同时，计算出外部计数事件以获得计数事件值。然后接收并处理从模拟设计获得的仿真结果数据。在处理中，响应于确定偏移计数事件的计数事件值是否超过先前记录的计数事件值，将计数事件值记录在数据存储子系统内。

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