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61. 发明授权

US08987114B2 Bonded semiconductor structures and method of forming same 有权
标题翻译：结合半导体结构及其形成方法
公开(公告)号：US08987114B2
公开(公告)日：2015-03-24
申请号：US13637565
申请日：2011-02-22
申请人： Carlos Mazure , Bich-Yen Nguyen , Mariam Sadaka
发明人： Carlos Mazure , Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： H01L21/00 , H01L27/06 , H01L21/18 , H01L21/822 , H01L21/02
CPC分类号： H01L27/0688 , H01L21/02532 , H01L21/0262 , H01L21/02667 , H01L21/187 , H01L21/8221 , H01L2924/00011 , H01L2224/80001
摘要： Methods of forming semiconductor structures include transferring a portion (116a) of a donor structure to a processed semiconductor structure (102) that includes at least one non-planar surface. An amorphous film (144) may be formed over at least one non-planar surface of the bonded semiconductor structure, and the amorphous film may be planarized to form one or more planarized surfaces. Semiconductor structures include a bonded semiconductor structure having at least one non-planar surface, and an amorphous film disposed over the at least one non-planar surface. The bonded semiconductor structure may include a processed semiconductor structure and a portion of a single crystal donor structure attached to a non-planar surface of the processed semiconductor structure.
摘要翻译：形成半导体结构的方法包括将施主结构的部分（116a）转移到包括至少一个非平面表面的经处理的半导体结构（102）。可以在结合的半导体结构的至少一个非平面表面上形成非晶膜（144），并且可以将非晶膜平坦化以形成一个或多个平坦化表面。半导体结构包括具有至少一个非平面表面的键合半导体结构和设置在所述至少一个非平面表面上的非晶膜。键合的半导体结构可以包括处理的半导体结构和附接到处理的半导体结构的非平面表面的单晶体施主结构的一部分。

62. 发明授权

US08455938B2 Device comprising a field-effect transistor in a silicon-on-insulator 有权
标题翻译：装置包括绝缘体上硅中的场效应晶体管
公开(公告)号：US08455938B2
公开(公告)日：2013-06-04
申请号：US12886421
申请日：2010-09-20
申请人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
发明人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
IPC分类号： H01L29/788 , H01L27/12
CPC分类号： H01L21/823462 , H01L21/823481 , H01L21/84 , H01L27/0705 , H01L27/1203 , H01L27/1207 , H01L29/7881
摘要： The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.
摘要翻译：本发明涉及一种具有绝缘体上半导体（SeOI）结构的半导体器件，其包括衬底，绝缘层如衬底上的氧化物层和具有场效应的绝缘层上的半导体层 - 晶体管（FET），其从所述衬底和沉积层形成在所述SeOI结构中，其中所述FET在所述衬底中具有沟道区;栅极介电层，其由所述SeOI结构的所述氧化物层的至少一部分制成; 以及至少部分地由SeOI结构的半导体层的一部分形成的栅电极。本发明还涉及从绝缘体上半导体结构形成一个或多个场效应晶体管或金属氧化物半导体晶体管的方法，该方法包括图案化和蚀刻SeOI结构，形成浅沟槽隔离，沉积绝缘金属或半导体层，以及去除掩模和/或图案层。

63. 发明授权

US08325506B2 Devices and methods for comparing data in a content-addressable memory 有权
标题翻译：用于比较内容可寻址存储器中的数据的装置和方法
公开(公告)号：US08325506B2
公开(公告)日：2012-12-04
申请号：US12974916
申请日：2010-12-21
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , H04L45/7453
摘要： The invention provides a content-addressable memory cell formed by two transistors that are configured so that one of the transistors is for storing a data bit and the other for is storing the complement of the data bit. Each transistor has a back control gate that can be controlled to block the associated transistor. The device also includes a comparison circuit that is configured to operate the first and second transistors in read mode while controlling the back control gate of each of the transistors so as to block the passing transistor if a proposed bit and the stored bit correspond. Then, the presence or absence of current on a source line linked to the source of each of the transistors indicates whether the proposed bit and the stored bit are identical or not. The invention also provides methods for operating the content-addressable memory cells of this invention, as well as content-addressable memories having a plurality of the content-addressable memory cells of this invention.
摘要翻译：本发明提供一种由两个晶体管形成的可内容寻址的存储单元，其被配置为使晶体管中的一个用于存储数据位，而另一个用于存储数据位的补码。每个晶体管具有可控制的阻挡相关晶体管的反向控制栅极。该器件还包括比较电路，其被配置为在读取模式下操作第一和第二晶体管，同时控制每个晶体管的反向控制栅极，以便如果所提出的位和存储的位对应，则阻止通过晶体管。然后，连接到每个晶体管的源极的源极线上的电流的存在或不存在指示所提出的位和存储的位是否相同。本发明还提供了用于操作本发明的内容可寻址存储器单元的方法，以及具有多个本发明的可内容寻址存储单元的可内容寻址存储器。

64. 发明授权

US08223582B2 Pseudo-inverter circuit on SeOI 有权
标题翻译： SeOI上的伪逆变电路
公开(公告)号：US08223582B2
公开(公告)日：2012-07-17
申请号：US12793553
申请日：2010-06-03
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

65. 发明授权

US08013417B2 Low cost substrates and method of forming such substrates 有权
标题翻译：低成本基板和形成这种基板的方法
公开(公告)号：US08013417B2
公开(公告)日：2011-09-06
申请号：US12469436
申请日：2009-05-20
申请人： Bich-Yen Nguyen , Carlos Mazure
发明人： Bich-Yen Nguyen , Carlos Mazure
IPC分类号： H01L21/70
CPC分类号： H01L21/76256 , H01L21/76254 , Y10T428/24851
摘要： In one embodiment, the invention provides engineered substrates having a support with surface pits, an intermediate layer of amorphous material arranged on the surface of the support so as to at least partially fill the surface pits, and a top layer arranged on the intermediate layer. The invention also provides methods for manufacturing the engineered substrates which deposit an intermediate layer on a pitted surface of a support so as to at least partially fill the surface pits, then anneal the intermediate layer, then assemble a donor substrate with the annealed intermediate layer to form an intermediate structure, and finally reduce the thickness of the donor substrate portion of the intermediate structure in order to form the engineered substrate.
摘要翻译：在一个实施例中，本发明提供了具有表面凹坑的支撑件的工程衬底，布置在支撑件表面上以至少部分地填充表面凹坑的非晶材料的中间层以及布置在中间层上的顶层。本发明还提供了用于制造工程衬底的方法，其将中间层沉积在支撑体的凹坑表面上，以便至少部分地填充表面凹坑，然后退火中间层，然后将施加衬底与退火的中间层组装成形成中间结构，并且最终减小中间结构的施主衬底部分的厚度以形成工程衬底。

66. 发明申请

US20110170343A1 DRAM MEMORY CELL HAVING A VERTICAL BIPOLAR INJECTOR 有权
标题翻译：具有垂直双极性注射器的DRAM存储单元
公开(公告)号：US20110170343A1
公开(公告)日：2011-07-14
申请号：US12942754
申请日：2010-11-09
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G11C11/40 , H01L29/786
CPC分类号： H01L29/7841 , G11C11/404 , G11C2211/4016 , H01L27/0711 , H01L27/10802 , H01L29/086 , H01L29/7302
摘要： The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.
摘要翻译：本发明涉及具有源极，漏极和源极和漏极之间的浮体的FET晶体管的存储单元，以及可以被控制以将电荷注入到FET晶体管的浮动体中的注入器。注射器包括具有由FET晶体管的主体形成的发射极，基极和集电极的双极晶体管。具体地说，在存储单元中，双极型晶体管的发射极配置成使FET晶体管的源极作为双极晶体管的基极。本发明还包括包括根据本发明的第一方面的多个存储器单元的存储器阵列以及控制这种存储器单元的方法。

67. 发明申请

US20110170327A1 DEVICES AND METHODS FOR COMPARING DATA IN A CONTENT-ADDRESSABLE MEMORY 有权
标题翻译：用于比较内容可寻址存储器中的数据的设备和方法
公开(公告)号：US20110170327A1
公开(公告)日：2011-07-14
申请号：US12974916
申请日：2010-12-21
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G11C15/04 , H01L27/12
CPC分类号： G11C15/046 , H04L45/7453
摘要： The invention provides a content-addressable memory cell formed by two transistors that are configured so that one of the transistors is for storing a data bit and the other for is storing the complement of the data bit. Each transistor has a back control gate that can be controlled to block the associated transistor. The device also includes a comparison circuit that is configured to operate the first and second transistors in read mode while controlling the back control gate of each of the transistors so as to block the passing transistor if a proposed bit and the stored bit correspond. Then, the presence or absence of current on a source line linked to the source of each of the transistors indicates whether the proposed bit and the stored bit are identical or not. The invention also provides methods for operating the content-addressable memory cells of this invention, as well as content-addressable memories having a plurality of the content-addressable memory cells of this invention.
摘要翻译：本发明提供一种由两个晶体管形成的可内容寻址的存储单元，其被配置为使晶体管中的一个用于存储数据位，而另一个用于存储数据位的补码。每个晶体管具有可控制的阻挡相关晶体管的反向控制栅极。该器件还包括比较电路，其被配置为在读取模式下操作第一和第二晶体管，同时控制每个晶体管的反向控制栅极，以便如果所提出的位和存储的位对应，则阻止通过晶体管。然后，连接到每个晶体管的源极的源极线上的电流的存在或不存在指示所提出的位和存储的位是否相同。本发明还提供了用于操作本发明的内容可寻址存储器单元的方法，以及具有多个本发明的可内容寻址存储单元的可内容寻址存储器。

68. 发明申请

US20110133776A1 ARRAYS OF TRANSISTORS WITH BACK CONTROL GATES BURIED BENEATH THE INSULATING FILM OF A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 有权
标题翻译：具有后控制栅的晶体管阵列BENEATH BENEATH半导体绝缘体衬底的绝缘膜
公开(公告)号：US20110133776A1
公开(公告)日：2011-06-09
申请号：US12961293
申请日：2010-12-06
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： H03K19/173 , H01L27/12 , H03K3/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11807
摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.
摘要翻译：本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上并且包括一组图案，每个图案由至少一个场效应晶体管形成，每个FET晶体管在薄膜中，源极区域，漏极区域，沟道区域和形成在沟道区域上方的前部控制栅极区域。所提供的器件还包括至少一个FET晶体管，其具有包括形成在沟道区域下方的基底衬底中的反向控制栅极区域的图案，所述背栅极区域能够被偏置以便移位晶体管的阈值电压以模拟晶体管的沟道宽度的修改或迫使晶体管保持关断或者在其前控制栅上施加的任何电压。本发明还提供了操作这种半导体器件结构的方法。

69. 发明申请

US20110042780A1 METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES OBTAINED BY SUCH METHODS 审中-公开
标题翻译：制造半导体结构的方法和采用这种方法获得的半导体结构
公开(公告)号：US20110042780A1
公开(公告)日：2011-02-24
申请号：US12989532
申请日：2009-05-18
申请人： Bich-Yen Nguyen , Carlos Mazure
发明人： Bich-Yen Nguyen , Carlos Mazure
IPC分类号： H01L21/30 , H01L29/02
CPC分类号： H01L21/76254 , H01L21/76256
摘要： In preferred embodiments, this invention provides a semiconductor structure that has a semi-conducting support, an insulating layer arranged on a portion of the support and a semi-conducting superficial layer arranged on the insulating layer. Electronic devices can be formed in the superficial layer and also in the exposed portion of the semi-conducting bulk region of the substrate not covered by the insulating layer. The invention also provides methods of fabricating such semiconductor structures which, starting from a substrate that includes a semi-conducting superficial layer arranged on a continuous insulating layer both of which being arranged on a semi-conducting support, by transforming at least one selected region of a substrate so as to form an exposed semi-conducting bulk region of the substrate.
摘要翻译：在优选实施例中，本发明提供一种半导体结构，其具有半导电支撑件，布置在支撑件的一部分上的绝缘层和布置在绝缘层上的半导电表面层。电子器件可以形成在表面层中，也可以形成在衬底的半导体本体区域的未被绝缘层覆盖的露出部分中。本发明还提供了制造这样的半导体结构的方法，其从包括布置在连续绝缘层上的半导电表面层的衬底开始，两者均布置在半导电支撑件上，通过将至少一个选定区域基板，以形成基板的暴露的半导体本体区域。

70. 发明申请

US20110012200A1 SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER 有权
标题翻译：具有绝缘层的充电区的基底
公开(公告)号：US20110012200A1
公开(公告)日：2011-01-20
申请号：US12865838
申请日：2008-03-13
申请人： Frederic Allibert , Gweltaz Gaudin , Fabrice Lallement , Didier Landru , Karine Landry , Mohamad Shaheen , Carlos Mazure
发明人： Frederic Allibert , Gweltaz Gaudin , Fabrice Lallement , Didier Landru , Karine Landry , Mohamad Shaheen , Carlos Mazure
IPC分类号： H01L27/12 , H01L21/30 , H01L21/02
CPC分类号： H01L29/78603 , H01L29/32 , H01L29/7841 , H01L31/0248
摘要： Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
摘要翻译：本发明的实施例涉及包括基底晶片，绝缘层和顶部半导体层的基板，其中绝缘层至少包括电荷密度高于1010电荷/ cm 2的绝对值的区域。本发明还涉及制造这种基材的方法。

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