专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07114042B2 Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment 有权
标题翻译：在非对称异构多处理器环境中提供原子更新原语的方法
公开(公告)号：US07114042B2
公开(公告)日：2006-09-26
申请号：US10443727
申请日：2003-05-22
申请人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichum Peter Liu , Thuong Quang Truong
发明人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichum Peter Liu , Thuong Quang Truong
IPC分类号： G06F13/00
CPC分类号： G06F13/28 , G06F9/3004 , G06F9/30087 , G06F12/0831 , G06F2213/0038
摘要： The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.
摘要翻译：本发明提供了具有具有DMA传输的共享存储器的非对称单芯片异构多处理器计算机系统中的原子更新原语。从包括具有预留的get lock line命令，put lock line条件命令和put lock line无条件命令的集合中生成至少一个lock line命令。

62. 发明授权

US06931493B2 Implementation of an LRU and MRU algorithm in a partitioned cache 有权
标题翻译：在分区缓存中实现LRU和MRU算法
公开(公告)号：US06931493B2
公开(公告)日：2005-08-16
申请号：US10346294
申请日：2003-01-16
申请人： Charles Ray Johns , James Allan Kahle , Peichun Peter Liu
发明人： Charles Ray Johns , James Allan Kahle , Peichun Peter Liu
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F12/123 , G06F12/128
摘要： The present invention provides for determining an MRU or LRU way of a partitioned cache. The partitioned cache has a plurality of ways. There are a plurality of partitions, each partition comprising at least one way. An updater is employable to update a logic table as a function of an access of a way. Partition comparison logic is employable to determine whether two ways are members of the same partition, and to allow the comparison of the ways correlating to a first matrix indices and a second matrix indices. An intersection generator is employable to create an intersection box of the memory table as a function of a first and second matrix indices. Access order logic is employable to combine the output of the intersection generator, thereby determining which way is the most or least recently used way.
摘要翻译：本发明提供用于确定分区高速缓存的MRU或LRU方式。分区缓存具有多种方式。存在多个分区，每个分区包括至少一个方式。更新器可用于根据方式的访问来更新逻辑表。分区比较逻辑可用于确定两种方式是否是相同分区的成员，并且允许比较与第一矩阵索引和第二矩阵索引相关的方式。交叉点生成器可用于根据第一和第二矩阵索引创建存储表的交集框。访问顺序逻辑可用于组合交叉发生器的输出，从而确定哪种方式是最近或最近最少使用的方式。

63. 发明授权

US06725354B1 Shared execution unit in a dual core processor 有权
标题翻译：共享执行单元在双核处理器中
公开(公告)号：US06725354B1
公开(公告)日：2004-04-20
申请号：US09594631
申请日：2000-06-15
申请人： James Allan Kahle , Charles Roberts Moore
发明人： James Allan Kahle , Charles Roberts Moore
IPC分类号： G06F900
CPC分类号： G06F9/3017 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3879 , G06F9/3885 , G06F15/7832
摘要： A microprocessor includes a first processor core and a second processor core. The first core includes a first processing block. The first processing block includes an execution unit suitable for executing a first type of instruction. The second core includes a second processing block. The second processing block includes an execution unit suitable for executing an instruction if the instruction is of the first type. The processor further includes a shared execution unit. The first and second processor cores are adapted to forward an instruction to the shared execution unit for execution if the instruction is of a second type. In one embodiment, the first type of instruction includes fixed point instructions, load/store instructions, and branch instructions and the second type of instruction includes floating point instructions.
摘要翻译：微处理器包括第一处理器核和第二处理器核。第一核心包括第一处理块。第一处理块包括适于执行第一类型的指令的执行单元。第二核心包括第二处理块。第二处理块包括执行单元，如果指令是第一类型，则适合于执行指令。处理器还包括共享执行单元。如果指令是第二类型，则第一和第二处理器核心适于将指令转发到共享执行单元以执行。在一个实施例中，第一类型的指令包括固定点指令，加载/存储指令和分支指令，并且第二类型的指令包括浮点指令。

64. 发明授权

US06631463B1 Method and apparatus for patching problematic instructions in a microprocessor using software interrupts 有权
标题翻译：使用软件中断在微处理器中修补有问题的指令的方法和装置
公开(公告)号：US06631463B1
公开(公告)日：2003-10-07
申请号：US09436103
申请日：1999-11-08
申请人： Michael Stephen Floyd , James Allan Kahle , Hung Qui Le , John Anthony Moore , Kevin Franklin Reick , Edward John Silha
发明人： Michael Stephen Floyd , James Allan Kahle , Hung Qui Le , John Anthony Moore , Kevin Franklin Reick , Edward John Silha
IPC分类号： G06F900
CPC分类号： G06F9/382 , G06F9/3017 , G06F9/3802 , G06F9/3861
摘要： A method and apparatus for patching a problematic instruction within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate a matched instruction. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. A matched instruction may be marked using a match bit that accompanies the instruction through the instruction pipeline. The matched instruction is then replaced with an internal opcode or internal instruction that causes the instruction scheduling unit to take a special software interrupt. The problematic instruction is then patched through the execution of a set of instructions that cause the desired logical operation of the problematic instruction.
摘要翻译：提出了一种用于在数据处理系统中的流水线处理器内修补有问题的指令的方法和装置。获取多个指令，并且将多个指令与至少一个匹配条件进行匹配以生成匹配的指令。匹配条件可以包括匹配指令的操作码，指令的预解码位，指令的类型或其他条件。可以使用伴随指令的匹配位通过指令流水线来标记匹配指令。匹配的指令被替换为内部操作码或内部指令，使指令调度单元进行特殊的软件中断。然后通过执行导致有问题的指令的期望的逻辑操作的一组指令来修补有问题的指令。

65. 发明授权

US06473850B1 System and method for handling instructions occurring after an ISYNC instruction 失效
标题翻译：用于以程序顺序有选择地刷新遵循ISYNC屏障指令的指令的系统
公开(公告)号：US06473850B1
公开(公告)日：2002-10-29
申请号：US09389197
申请日：1999-09-02
申请人： Hoichi Cheong , R. William Hay , James Allan Kahle , Hung Qui Le
发明人： Hoichi Cheong , R. William Hay , James Allan Kahle , Hung Qui Le
IPC分类号： G06F938
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3834
摘要： An ISYNC instruction does not cause a flush of speculatively dispatched or fetched instructions (instructions that are dispatched or fetched after the ISYNC instruction) unconditionally. The present invention detects the occurrence of any instruction that changes the state of the machine and requires a context synchronizing complete; these instructions are called context-synchronizing-required instructions. When a context-synchronizing-required instruction completes, the present invention sets a flag to note the occurrence of that condition. When an ISYNC instruction completes, the present invention causes a flush and refetches the instruction after the ISYNC if the context-synchronizing-required flag is active. The present invention then resets the context-synchronizing-required flag. If the context-synchronizing-required flag is not active, then the present invention does not generate a flush operation.
摘要翻译： ISYNC指令不会导致无条件地抛出推测分派或获取的指令（在ISYNC指令之后调度或取出的指令）。本发明检测改变机器状态并需要上下文同步完成的任何指令的发生; 这些指令称为上下文同步所需指令。当上下文同步所需指令完成时，本发明设置一个标志以注意该条件的发生。当ISYNC指令完成时，如果上下文同步所需的标志是活动的，本发明引起冲洗并在ISYNC之后重新指定该指令。然后，本发明重置上下文同步所需标志。如果上下文同步所需的标志不是活动的，则本发明不产生刷新操作。

66. 发明授权

US06460115B1 System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism 有权
标题翻译：用于将数据预取到多级缓存的系统和方法，包括选择性地使用软件提示来覆盖硬件预取机制
公开(公告)号：US06460115B1
公开(公告)日：2002-10-01
申请号：US09435865
申请日：1999-11-08
申请人： James Allan Kahle , Michael John Mayfield , Francis Patrick O'Connell , David Scott Ray , Edward John Silha , Joel Tendler
发明人： James Allan Kahle , Michael John Mayfield , Francis Patrick O'Connell , David Scott Ray , Edward John Silha , Joel Tendler
IPC分类号： G06F1300
CPC分类号： G06F9/3802 , G06F9/30047 , G06F9/383 , G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of cache lines is concurrently performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches are performed over a private or dedicated prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction or hint may be used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine.
摘要翻译：一种用于在多级代码子系统中预取数据的数据处理系统和方法。数据处理系统包括具有第一级高速缓存和预取引擎的处理器。耦合到处理器的是第二级缓存，以及第三级缓存和系统存储器。通过预取引擎将高速缓存行预取同时执行到第一，第二和第三级高速缓存中的每一个。从预取引擎到第二级和第三级高速缓存的预取请求通过私有或专用预取请求总线执行，该专用或专用预取请求总线与将数据从各种高速缓存级别传送到处理器的总线系统分开。软件指令或提示可用于通过覆盖硬件预取引擎的正常功能来加速预取过程。

67. 发明授权

US06430678B1 Scoreboard mechanism for serialized string operations utilizing the XER 失效
标题翻译：使用XER的串行字符串操作的记分板机制
公开(公告)号：US06430678B1
公开(公告)日：2002-08-06
申请号：US09363463
申请日：1999-07-29
申请人： James Allan Kahle , Hung Qui Le , Lee Evan Eisen , John Edward Derrick , Robert William Hay
发明人： James Allan Kahle , Hung Qui Le , Lee Evan Eisen , John Edward Derrick , Robert William Hay
IPC分类号： G06F930
CPC分类号： G06F9/30018 , G06F9/3017 , G06F9/325 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit to determine if the scoreboard bit is set. If the scoreboard bit is not set when the dummy read is executed, the X-form string proceeds to execution. If the scoreboard bit is set when the dummy is executed, the pipeline is stalled until the scoreboard bit is cleared, and then the X-form string padded with generated padding IOPs (Dummy or NOPs) is executed. After an accessing instruction is executed, the scoreboard bit is cleared.
摘要翻译：通过使用指令排序器单元记分板提供XER记分板功能。如果XER由前一条指令使用，记分板位将被置位。如果获取使用XER的新指令，则生成对XER的虚拟读取以测试记分板位以确定记分板位是否设置。如果执行虚拟读取时记分板位未设置，则X形式的字符串将继续执行。如果在执行虚拟机时设置了记分板位，则流水线停止，直到记分板位被清除，然后执行填充有生成的填充IOP（虚拟或NOP）的X形式字符串。执行访问指令后，记分板位被清除。

68. 发明授权

US5926628A Selectable priority bus arbitration scheme 失效
标题翻译：可选优先级总线仲裁方案
公开(公告)号：US5926628A
公开(公告)日：1999-07-20
申请号：US892723
申请日：1997-07-15
申请人： Cang Ngoc Tran , James Allan Kahle
发明人： Cang Ngoc Tran , James Allan Kahle
IPC分类号： G06F13/364 , G06F13/36
CPC分类号： G06F13/364
摘要： A method and system for arbitrating access to a component of a computer have been disclosed the method and system include an arbitration unit for granting access to the component; and a plurality of units for executing a plurality of transactions requiring access to the component. Each transaction of the plurality of transactions has an encoded priority. Each of the plurality of units further provide the arbitration unit with the encoded priority of each of the plurality of transactions. The arbitration unit grants a predetermined number of the plurality of units access to the component in response to the encoded priority of each of the predetermined plurality of transactions.
摘要翻译：已经公开了一种用于仲裁对计算机的组件的访问的方法和系统，所述方法和系统包括用于授予访问组件的仲裁单元; 以及用于执行需要访问该组件的多个事务的多个单元。多个事务的每个事务具有编码的优先级。多个单元中的每一个还向仲裁单元提供多个交易中的每一个的编码优先级。仲裁单元响应于每个预定多个事务的编码优先级，向该组件授予多个单元的预定数量的访问。

69. 发明授权

US5913044A Method and system for simultaneous variable-width bus access in a multiprocessor system 失效
标题翻译：在多处理器系统中同时进行可变宽度总线访问的方法和系统
公开(公告)号：US5913044A
公开(公告)日：1999-06-15
申请号：US933154
申请日：1997-09-18
申请人： Cang Ngoc Tran , James Allan Kahle
发明人： Cang Ngoc Tran , James Allan Kahle
IPC分类号： G06F13/364 , G06F13/14 , G06F13/00
CPC分类号： G06F13/364
摘要： A method and system for enhanced bus access in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a maximum-permitted number of sub-buses. If the number of sub-buses granted to a particular processor equals the number of pending transactions at that processor, all pending transactions are performed in parallel on separate sub-buses. If the number of sub-buses granted is less than the number of pending transactions, pending transactions are performed in a priority order. Finally, if the number of granted sub-buses is greater than the number of pending transactions, selected transactions are performed over multiple sub-buses in parallel, greatly enhancing the speed of those transactions.
摘要翻译：一种在具有通过公共宽总线耦合到系统存储器的多处理器的多处理器系统中用于增强总线访问的方法和系统。公共宽总线被细分为多个子总线，其可以由所选择的处理器单独或分组访问，或者各个子总线可以由多个处理器同时访问。响应于一个或多个待处理的事务，每个处理器输出对总线仲裁逻辑的请求以允许最大允许数量的子总线。如果授予特定处理器的子总线数量等于该处理器中未决事务的数量，则所有挂起的事务将在单独的子总线上并行执行。如果授权的子总线数量少于待处理的事务数量，则按优先级顺序执行待处理事务。最后，如果授权子总线的数量大于未决事务的数量，则选择的事务并行执行多个子总线，大大提高了这些事务的速度。

70. 发明授权

US5748938A System and method for maintaining coherency of information transferred between multiple devices 失效
标题翻译：用于维护在多个设备之间传送的信息的一致性的系统和方法
公开(公告)号：US5748938A
公开(公告)日：1998-05-05
申请号：US350399
申请日：1994-12-06
申请人： James Allan Kahle
发明人： James Allan Kahle
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0835
摘要： A method and system are provided for maintaining memory coherency. A first device stores information. A second device is coupled to the first device. The second device inputs at least a portion of the information and outputs an indication that the portion is not to be cached by the second device. Rather than initializing other devices to "know" in advance that a cache memory is absent from a given device, a control signal indicates the device's intent to not cache the requested portion of information in a cache memory.
摘要翻译：提供了一种用于维持存储器一致性的方法和系统。第一个设备存储信息。第二设备耦合到第一设备。第二设备输入信息的至少一部分并输出该部分不被第二设备高速缓存的指示。事先将其他设备初始化为“知道”，从给定设备中不存在高速缓冲存储器，控制信号指示设备不希望将所请求的部分信息缓存在高速缓冲存储器中的意图。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式