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61. 发明授权

US08261025B2 Software pipelining on a network on chip 失效
标题翻译：软件流水线在片上网络上
公开(公告)号：US08261025B2
公开(公告)日：2012-09-04
申请号：US11938376
申请日：2007-11-12
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F15/00 , G06F9/30
CPC分类号： H04L49/15 , H04L49/109 , H04L49/252 , H04L49/3036 , H04L49/90 , H04L49/901
摘要： Memory sharing in a software pipeline on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution; allocating memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated; determining, in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and deallocating the shared memory.
摘要翻译：在芯片上的软件管道（“NOC”）中的内存共享，NOC包括集成处理器（IP）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器，其中每个存储器通信控制器控制IP块和存储器之间的通信以及控制通过路由器进行IP间块通信的每个网络接口控制器，包括将计算机软件应用程序分段成软件流水线的阶段，所述软件流水线包括一个或多个执行路径; 在至少两个阶段中分配要共享的存储器，包括创建智能指针，所述智能指针包括用于确定何时可以释放所述共享存储器的数据元素; 根据用于确定何时可以释放共享存储器的数据元素确定可以释放共享存储器; 并释放共享内存。

62. 发明申请

US20120192202A1 Context Switching On A Network On Chip 审中-公开
标题翻译：上下文切换网络芯片
公开(公告)号：US20120192202A1
公开(公告)日：2012-07-26
申请号：US13440589
申请日：2012-04-05
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F9/46
CPC分类号： G06F15/7825 , H04L49/109
摘要： A network on chip (NOC) that includes IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to the network by an application messaging interconnect including an inbox and an outbox, one or more of the IP blocks including computer processors supporting a plurality of threads, the NOC also including an inbox and outbox controller configured to set pointers to the inbox and outbox, respectively, that identify valid message data for a current thread; and software running in the current thread that, upon a context switch to a new thread, is configured to: save the pointer values for the current thread, and reset the pointer values to identify valid message data for the new thread, where the inbox and outbox controller are further configured to retain the valid message data for the current thread in the boxes until context switches again to the current thread.
摘要翻译：包括IP块，路由器，存储器通信控制器和网络接口控制器的片上网络（NOC），每个IP块通过包括收件箱和发件箱的应用消息传送互连网络适配于网络，所述IP块中的一个或多个包括支持多个线程的计算机处理器，NOC还包括分别设置用于标识当前线程的有效消息数据的收件箱和发送箱的指针的收件箱和发送箱控制器; 以及在当前线程中运行的软件，在上下文切换到新线程时，配置为：保存当前线程的指针值，并重置指针值以识别新线程的有效消息数据，其中收件箱和发送箱控制器被进一步配置为将当前线程的有效消息数据保留在框中，直到上下文再次切换到当前线程。

63. 发明授权

US08214845B2 Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data 有权
标题翻译：通过线程保存和恢复指向包含有效消息数据的存储器阵列的指针，片上网络中的上下文切换
公开(公告)号：US08214845B2
公开(公告)日：2012-07-03
申请号：US12118039
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F9/46 , G06F13/00 , G06F9/00
CPC分类号： G06F15/7825 , H04L49/109
摘要： A network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to the network by an application messaging interconnect including an inbox and an outbox, one or more of the IP blocks including computer processors supporting a plurality of threads, the NOC also including an inbox and outbox controller configured to set pointers to the inbox and outbox, respectively, that identify valid message data for a current thread; and software running in the current thread that, upon a context switch to a new thread, is configured to: save the pointer values for the current thread, and reset the pointer values to identify valid message data for the new thread, where the inbox and outbox controller are further configured to retain the valid message data for the current thread in the boxes until context switches again to the current thread.
摘要翻译：包括IP块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过包括收件箱和发件箱的应用消息传送互连网络适配到网络，IP网络中的一个或多个块，包括支持多个线程的计算机处理器，NOC还包括分别设置指向当前线程的有效消息数据的收件箱和发送箱的指针的收件箱和发件箱控制器; 以及在当前线程中运行的软件，在上下文切换到新线程时，配置为：保存当前线程的指针值，并重置指针值以识别新线程的有效消息数据，其中收件箱和发送箱控制器被进一步配置为将当前线程的有效消息数据保留在框中，直到上下文再次切换到当前线程。

64. 发明授权

US08140832B2 Single step mode in a software pipeline within a highly threaded network on a chip microprocessor 失效
标题翻译：芯片微处理器高线程网络中的软件流水线中的单步模式
公开(公告)号：US08140832B2
公开(公告)日：2012-03-20
申请号：US12358776
申请日：2009-01-23
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F11/00
CPC分类号： G06F9/3844 , G06F9/30174 , G06F9/3806 , G06F11/3636 , G06F11/3648
摘要： A hardware thread is selectively forced to single step the execution of software instructions from a work packet granule. A “single step” packet is associated with a work packet granule. The work packet granule, with the associated “single step” packet, is dispatched as an appended work packet granule to a preselected hardware thread in a processor core, which, in one embodiment, is located at a node in a Network On a Chip (NOC). The work packet granule then executes in a single step mode until completion.
摘要翻译：有选择地强制硬件线程从工作包颗粒单步执行软件指令。 “单步”包与工作包颗粒相关联。具有相关联的“单步”分组的工作分组粒子被作为附加的工作分组粒子被分派到处理器核心中的预选硬件线程，在一个实施例中，其在一个实施例中位于网络片上（ NOC）。工作包颗粒然后以单步模式执行直到完成。

65. 发明授权

US08108908B2 Security methodology to prevent user from compromising throughput in a highly threaded network on a chip processor 失效
标题翻译：防止用户在芯片处理器高线程网络中吞吐量的安全方法
公开(公告)号：US08108908B2
公开(公告)日：2012-01-31
申请号：US12255818
申请日：2008-10-22
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F7/04 , G06F17/30 , G06F15/16 , H04L29/06 , G06F13/00
CPC分类号： G06F21/74
摘要： A computer-implemented method, system and computer program product for preventing an untrusted work unit message from compromising throughput in a highly threaded Network On a Chip (NOC) processor are presented. A security message, which is associated with the untrusted work unit message, directs other resources within the NOC to operate in a secure mode while a specified node, within the NOC, executes instructions from the work unit message in a less privileged non-secure mode. Thus, throughput within the NOC is uncompromised due to resources, other than the first node, being protected from the untrusted work unit message.
摘要翻译：提出了一种计算机实现的方法，系统和计算机程序产品，用于防止不可信的工作单元消息危及高度线程的片上网络（NOC）处理器中的吞吐量。与不受信任的工作单元消息相关联的安全消息指示NOC内的其他资源以安全模式操作，而NOC内的指定节点以较不特权的非安全模式执行来自工作单元消息的指令。因此，除了第一节点之外的资源被保护以防止不受信任的工作单元消息，NOC内的吞吐量是不妥协的。

66. 发明申请

US20110321049A1 Programmable Integrated Processor Blocks 失效
标题翻译：可编程集成处理器模块
公开(公告)号：US20110321049A1
公开(公告)日：2011-12-29
申请号：US12823745
申请日：2010-06-25
申请人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/46 , G06F9/318
CPC分类号： G06F15/7825 , G06F9/3879
摘要： An integrated processor block of the network on a chip is programmable to perform a first function. The integrated processor block includes an inbox to receive incoming packets from other integrated processor blocks of a network on a chip, an outbox to send outgoing packets to the other integrated processor blocks, an on-chip memory, and a memory management unit to enable access to the on-chip memory.
摘要翻译：芯片上的网络的集成处理器块可编程以执行第一功能。集成处理器块包括用于从芯片上的网络的其他集成处理器块接收传入分组的收件箱，向其他集成处理器块发送输出分组的发送箱，片上存储器和存储器管理单元，以使得能够访问到片上存储器。

67. 发明申请

US20110320719A1 PROPAGATING SHARED STATE CHANGES TO MULTIPLE THREADS WITHIN A MULTITHREADED PROCESSING ENVIRONMENT 有权
标题翻译：在多重加工环境中传播多种螺纹的共享状态变化
公开(公告)号：US20110320719A1
公开(公告)日：2011-12-29
申请号：US12824778
申请日：2010-06-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06T15/005
摘要： A circuit arrangement and method make state changes to shared state data in a highly multithreaded environment by propagating or streaming the changes to multiple parallel hardware threads of execution in the multithreaded environment using an on-chip communications network and without attempting to access any copy of the shared state data in a shared memory to which the parallel threads of execution are also coupled. Through the use of an on-chip communications network, changes to the shared state data may be communicated quickly and efficiently to multiple threads of execution, enabling those threads to locally update their local copies of the shared state. Furthermore, by avoiding attempts to access a shared memory, the interface to the shared memory is not overloaded with concurrent access attempts, thus preserving memory bandwidth for other activities and reducing memory latency. Particularly for larger shared states, propagating the changes, rather than an entire shared state, further improves performance by reducing the amount of data communicated over the on-chip communications network.
摘要翻译：电路布置和方法通过使用片上通信网络在多线程环境中传播或将变化传播或传输到多个并行硬件执行线程而不尝试访问任何副本，从而使状态对高度多线程环境中的共享状态数据进行改变并行线程执行的共享存储器中的共享状态数据也被耦合。通过使用片上通信网络，可以将共享状态数据的改变快速且有效地传送到多个执行线程，使得这些线程能够本地更新其共享状态的本地副本。此外，通过避免访问共享内存的尝试，共享内存的接口不会因并发访问尝试而过载，从而保留其他活动的内存带宽并减少内存延迟。特别是对于较大的共享状态，传播改变而不是整个共享状态，通过减少通过片上通信网络传送的数据量来进一步提高性能。

68. 发明申请

US20110316864A1 MULTITHREADED SOFTWARE RENDERING PIPELINE WITH DYNAMIC PERFORMANCE-BASED REALLOCATION OF RASTER THREADS 失效
标题翻译：多功能软件渲染管道，具有基于性能的RASTER螺纹重载
公开(公告)号：US20110316864A1
公开(公告)日：2011-12-29
申请号：US12824727
申请日：2010-06-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： A multithreaded rendering software pipeline architecture dynamically reallocates regions of an image space to raster threads based upon performance data collected by the raster threads. The reallocation of the regions typically includes resizing the regions assigned to particular raster threads and/or reassigning regions to different raster threads to better balance the relative workloads of the raster threads.
摘要翻译：多线程渲染软件流水线架构基于栅格线程收集的性能数据，将图像空间的区域动态重新分配给栅格线程。区域的重新分配通常包括调整分配给特定光栅线程的区域和/或重新分配区域到不同的光栅线程，以更好地平衡光栅线程的相对工作负载。

69. 发明申请

US20110316855A1 Parallelized Streaming Accelerated Data Structure Generation 失效
标题翻译：并行流加速数据结构生成
公开(公告)号：US20110316855A1
公开(公告)日：2011-12-29
申请号：US12822427
申请日：2010-06-24
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06T17/00
CPC分类号： G06T15/06 , G06T2200/28 , G06T2210/52
摘要： A method includes receiving at a master processing element primitive data that includes properties of a primitive. The method includes partially traversing a spatial data structure that represents a three-dimensional image to identify an internal node of the spatial data structure. The internal node represents a portion of the three-dimensional image. The method also includes selecting a slave processing element from a plurality of slave processing elements. The selected processing element is associated with the internal node. The method further includes sending the primitive data to the selected slave processing element to traverse a portion of the spatial data structure to identify a leaf node of the spatial data structure.
摘要翻译：一种方法包括在主处理元件处接收包括原语的属性的原始数据。该方法包括部分地遍历表示三维图像以识别空间数据结构的内部节点的空间数据结构。内部节点表示三维图像的一部分。该方法还包括从多个从属处理元件中选择从属处理元件。所选择的处理元件与内部节点相关联。该方法还包括将原始数据发送到所选择的从属处理元件以遍历空间数据结构的一部分以识别空间数据结构的叶节点。

70. 发明授权

US08024616B2 Pseudo random process state register for fast random process test generation 失效
标题翻译：伪随机过程状态寄存器用于快速随机过程测试生成
公开(公告)号：US08024616B2
公开(公告)日：2011-09-20
申请号：US12359570
申请日：2009-01-26
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F11/00
CPC分类号： G06F11/263
摘要： A method, system and computer program product are presented for providing pseudo-random input test data to a test program. A seed value is generated and stored in a seed register. Using the seed value as an input, a pseudo-random input test value is generated by a Linear Feedback Shift Register (LFSR), and stored in a GPR within a processor core. Using the pseudo-random input test value from the GPR, a test program is executed within the processor core.
摘要翻译：提出了一种方法，系统和计算机程序产品，用于向测试程序提供伪随机输入测试数据。种子值生成并存储在种子寄存器中。使用种子值作为输入，通过线性反馈移位寄存器（LFSR）生成伪随机输入测试值，并存储在处理器核心内的GPR中。使用GPR中的伪随机输入测试值，在处理器核心内执行测试程序。

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