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61. 发明申请

US20090161442A1 Data Processing System 有权
标题翻译：数据处理系统
公开(公告)号：US20090161442A1
公开(公告)日：2009-06-25
申请号：US12085901
申请日：2005-12-02
申请人： David New , Paul Darren Hoxey , David Michael Bull , Shidhartha Das
发明人： David New , Paul Darren Hoxey , David Michael Bull , Shidhartha Das
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/24 , G11C11/4125 , G11C29/12 , G11C29/12005 , G11C29/26
摘要： A data processing system comprising a memory array having a plurality of memory cells (240-246) and read circuitry (310,320) for reading a logic value stored in one of the plurality of memory cells. The read circuitry (310,320) is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided (330) for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.
摘要翻译：一种数据处理系统，包括具有多个存储单元（240-246）和用于读取存储在所述多个存储单元之一中的逻辑值的读取电路（310,320）的存储器阵列。读取电路（310,320）可操作地执行存储的逻辑值的两个基本上同时的读取。提供电压控制器并且可操作以选择性地改变对存储器阵列的电源电压的电平。提供检测电路（330），用于根据两个基本上同时的读取来检测供电电压电平是否导致读取结果不可靠。

62. 发明申请

US20090106616A1 Integrated circuit using speculative execution 有权
标题翻译：集成电路采用推测执行
公开(公告)号：US20090106616A1
公开(公告)日：2009-04-23
申请号：US12285796
申请日：2008-10-14
申请人： Emre Ozer , David Michael Bull , Shidhartha Das
发明人： Emre Ozer , David Michael Bull , Shidhartha Das
IPC分类号： G06F11/07
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3869
摘要： An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.
摘要翻译：集成电路2设置有多个流水线级10.这些流水线级10具有推测性处理控制电路12，其允许下游流水线级的推测性处理，并且如果确定了这种推测性处理，则触发第一错误恢复操作（部分流水线冲洗）基于错误。流水线级10还包括推测性错误检测电路14，其产生关于处理电路18是否将产生错误的预测nc。该预测用于触发第二次错误恢复操作（部分流水线停止）。该第二错误恢复操作具有比第一错误恢复操作更低的性能损失。

63. 发明申请

US20080086624A1 Latch to block short path violation 有权
标题翻译：锁定阻止短路违规
公开(公告)号：US20080086624A1
公开(公告)日：2008-04-10
申请号：US11638703
申请日：2006-12-14
申请人： David Michael Bull , Shidhartha Das
发明人： David Michael Bull , Shidhartha Das
IPC分类号： G06F15/76
CPC分类号： G11C19/00
摘要： An integrated circuit 2 includes processing pipeline stages formed of an input register 8, processing circuit 10′, 10″ and an output register 12. The output register 12 employs speculative sampling and uses a subsequent speculation period during which any change in its input is detected and used to indicate a speculation error. In order to reduce the chances of a race condition giving rise to a false positive detection of a speculation error due to a too rapid signal propagation through the processing circuitry 10′, 10″, a transparent latch 14 is disposed at the approximate midpoint, measured in terms of propagation delay, within the processing circuitry 10′, 10″. This transparent latch 14 is non-transmissive during the speculation period of the output register 12 so as to prevent any new signal propagating from the input register 8 during the speculation period from reaching the output register 12.
摘要翻译：集成电路2包括由输入寄存器8，处理电路10'，10“和输出寄存器12形成的处理流水线级。输出寄存器12采用推测采样，并使用随后的推测周期，在此期间检测其输入中的任何变化并用于指示猜测误差。为了减少由于通过处理电路10'，10“的信号传播太快导致的猜测误差的假阳性检测的竞争条件的机会，透明锁存器14设置在大致中点处，在传播延迟方面测量，处理电路10'，10“内。该透明锁存器14在输出寄存器12的推测周期期间是非透射的，以便在推测期间防止任何新的信号从输入寄存器8传播到达输出寄存器12。

64. 发明授权

US06826670B2 Accessing memory units in a data processing apparatus 有权
标题翻译：访问数据处理设备中的存储器单元
公开(公告)号：US06826670B2
公开(公告)日：2004-11-30
申请号：US10158105
申请日：2002-05-31
申请人： Peter Guy Middleton , David Michael Bull , Gary Campbell
发明人： Peter Guy Middleton , David Michael Bull , Gary Campbell
IPC分类号： G06F1200
CPC分类号： G06F12/0888 , G06F12/0215 , Y02D10/13
摘要： The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access. Instead, prediction logic is arranged to predict the one or more predetermined attributes, and clock generation logic is responsive to the predictive predetermined attributes from the prediction logic to select which one of the memory units is to be clocked during performance of the access, and to issue a clock signal to that memory unit. Checking logic is then provided to determine whether the predetermined attributes generated by the attribute generation logic agree with the predicted predetermined attributes, and if not, to reinitiate the access, in which event the clock generation logic is arranged to reselect one of the memory units using the predetermined attributes as determined by the attribute generation logic. This approach enables high speed processing of access requests, whilst achieving significant power savings over prior art systems where multiple memory units are clocked speculatively in parallel.
摘要翻译：本发明涉及用于访问数据处理装置中的存储单元的技术。数据处理装置包括用于存储数据值的多个存储器单元，用于发出指定对数据值对存储器单元进行访问的访问请求的处理器核心，以及用于执行由数据值指定的访问的存储器控制器访问请求。提供属性生成逻辑用于从访问请求确定一个或多个预定属性，以便在执行访问时验证哪个存储单元应被使用。然而，存储器控制器不等待直到在开始访问之前由属性生成逻辑执行这样的确定。相反，预测逻辑被布置为预测一个或多个预定属性，并且时钟生成逻辑响应来自预测逻辑的预测预定属性，以选择在执行访问期间要计时的哪个存储器单元，以及向该存储单元发出时钟信号。然后提供检查逻辑以确定由属性生成逻辑生成的预定属性是否与预测的预定属性一致，如果不是，则重新启动访问，在哪种情况下，时钟生成逻辑被设置为使用由属性生成逻辑确定的预定属性。这种方法可以实现对访问请求的高速处理，同时相对于其中多个存储器单元并行地推测地计时的现有技术系统实现显着的功率节省。

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