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61. 发明授权

US5680482A Method and apparatus for improved video decompression by adaptive selection of video input buffer parameters 失效
标题翻译：用于通过视频输入缓冲器参数的自适应选择来改进视频解压缩的方法和装置
公开(公告)号：US5680482A
公开(公告)日：1997-10-21
申请号：US443206
申请日：1995-05-17
申请人： Yi Liu , Michael R. Tucker , Geoffrey S. Strongin
发明人： Yi Liu , Michael R. Tucker , Geoffrey S. Strongin
IPC分类号： G06T9/00 , H04N7/26 , H04N7/32 , H04N7/50 , G06K9/30 , H04N7/12
CPC分类号： H04N19/423 , H04N19/152 , H04N19/42 , H04N19/61 , H04N19/50
摘要： A video decompression system utilizes multiple independent input buffers so that input/output operations and processing take place concurrently, nearly continuously and at a rate that is substantially equal to a selected maximum access rate of the storage device. Consequently, the data rate of the video decompression system is optimized with respect to the rate of data accessing. The video decompression system adaptively sets input buffer parameters as a function, for example, of processor capabilities, bitstream characteristics, drive latency and access time, and file I/O overhead.
摘要翻译：视频解压缩系统利用多个独立的输入缓冲器，使得输入/输出操作和处理同时，几乎连续地并且以基本上等于存储设备的所选最大访问速率的速率进行。因此，视频解压缩系统的数据速率相对于数据访问速率被优化。视频解压缩系统自适应地将输入缓冲器参数设置为例如处理器能力，比特流特性，驱动器延迟和访问时间以及文件I / O开销的功能。

62. 发明申请

US20140157410A1 Secure Environment for Graphics Processing Units 有权
标题翻译：图形处理单元的安全环境
公开(公告)号：US20140157410A1
公开(公告)日：2014-06-05
申请号：US13690401
申请日：2012-11-30
申请人： Prashant Dewan , Uday R. Savagaonkar , David M. Durham , Paul S. Schmitz , Jason Martin , Michael Goldsmith , Ravi L. Sahita , Frank X McKeen , Carlos Rozas , Vembu Balaji , Scott Janus , Geoffrey S. Strongin , Xiaozhu Kang , Karanvir S. Grewal , Siddhartha Chhabra , Alpha T. Narendra Trivedi
发明人： Prashant Dewan , Uday R. Savagaonkar , David M. Durham , Paul S. Schmitz , Jason Martin , Michael Goldsmith , Ravi L. Sahita , Frank X McKeen , Carlos Rozas , Vembu Balaji , Scott Janus , Geoffrey S. Strongin , Xiaozhu Kang , Karanvir S. Grewal , Siddhartha Chhabra , Alpha T. Narendra Trivedi
IPC分类号： G06F21/64
CPC分类号： G06F21/64 , G06F21/53 , G06F21/56
摘要： In accordance with some embodiments, a protected execution environment may be defined for a graphics processing unit. This framework not only protects the workloads from malware running on the graphics processing unit but also protects those workloads from malware running on the central processing unit. In addition, the trust framework may facilitate proof of secure execution by measuring the code and data structures used to execute the workload. If a part of the trusted computing base of this framework or protected execution environment is compromised, that part can be patched remotely and the patching can be proven remotely throughout attestation in some embodiments.
摘要翻译：根据一些实施例，可以为图形处理单元定义受保护的执行环境。该框架不仅保护了图形处理单元上运行的恶意软件的工作负载，还保护了这些工作负载免受中央处理单元上运行的恶意软件。此外，信任框架可以通过测量用于执行工作负载的代码和数据结构来促进安全执行的证明。如果该框架或受保护的执行环境的可信计算基础的一部分受到损害，那么该部分可以被远程修补，并且在一些实施例中可以通过验证远程验证修补。

63. 发明申请

US20130283369A1 Providing A Multi-Phase Lockstep Integrity Reporting Mechanism 有权
标题翻译：提供多阶段锁步完整性报告机制
公开(公告)号：US20130283369A1
公开(公告)日：2013-10-24
申请号：US13925991
申请日：2013-06-25
申请人： Ned M. Smith , Vedvyas Shanbhogue , Geoffrey S. Strongin , Willard M. Wiseman , David W. Grawrock
发明人： Ned M. Smith , Vedvyas Shanbhogue , Geoffrey S. Strongin , Willard M. Wiseman , David W. Grawrock
IPC分类号： G06F21/44
CPC分类号： G06F21/44 , G06F21/50 , G06F21/57 , G06F21/575 , G06F21/85 , H04L63/126 , H04L67/125
摘要： In one embodiment, a processor can enforce a blacklist and validate, according to a multi-phase lockstep integrity protocol, a device coupled to the processor. Such enforcement may prevent the device from accessing one or more resources of a system prior to the validation. The blacklist may include a list of devices that have not been validated according to the multi-phase lockstep integrity protocol. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器可以强制黑名单并且根据多阶段锁步完整性协议验证耦合到处理器的设备。这种执行可以防止设备在验证之前访问系统的一个或多个资源。黑名单可以包括根据多阶段锁定完整性协议未被验证的设备的列表。描述和要求保护其他实施例。

64. 发明授权

US08516551B2 Providing a multi-phase lockstep integrity reporting mechanism 有权
标题翻译：提供多阶段锁步完整性报告机制
公开(公告)号：US08516551B2
公开(公告)日：2013-08-20
申请号：US12845528
申请日：2010-07-28
申请人： Ned M. Smith , Vedvyas Shanbhogue , Geoffrey S. Strongin , Willard M. Wiseman , David W. Grawrock
发明人： Ned M. Smith , Vedvyas Shanbhogue , Geoffrey S. Strongin , Willard M. Wiseman , David W. Grawrock
IPC分类号： G06F7/04
CPC分类号： G06F21/44 , G06F21/50 , G06F21/57 , G06F21/575 , G06F21/85 , H04L63/126 , H04L67/125
摘要： In one embodiment, a processor can enforce a blacklist and validate, according to a multi-phase lockstep integrity protocol, a device coupled to the processor. Such enforcement may prevent the device from accessing one or more resources of a system prior to the validation. The blacklist may include a list of devices that have not been validated according to the multi-phase lockstep integrity protocol. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器可以强制黑名单并且根据多阶段锁步完整性协议验证耦合到处理器的设备。这种执行可以防止设备在验证之前访问系统的一个或多个资源。黑名单可以包括根据多阶段锁定完整性协议未被验证的设备的列表。描述和要求保护其他实施例。

65. 发明授权

US07917726B2 Using an IOMMU to create memory archetypes 有权
标题翻译：使用IOMMU创建内存原型
公开(公告)号：US07917726B2
公开(公告)日：2011-03-29
申请号：US12685179
申请日：2010-01-11
申请人： Mark D. Hummel , Geoffrey S. Strongin , Andrew W. Lueck
发明人： Mark D. Hummel , Geoffrey S. Strongin , Andrew W. Lueck
IPC分类号： G06F12/10
CPC分类号： G06F12/1081 , G06F12/145 , G06F2212/656
摘要： In one embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory and control logic coupled to the memory. The memory is configured to store translation data corresponding to one or more I/O translation tables stored in a memory system of a computer system that includes the IOMMU. The control logic is configured to translate an I/O device-generated memory request using the translation data. The translation data includes a type field indicating one or more attributes of the translation, and the control logic is configured to control the translation responsive to the type field.
摘要翻译：在一个实施例中，输入/输出（I / O）存储器管理单元（IOMMU）包括耦合到存储器的至少一个存储器和控制逻辑。存储器被配置为存储对应于存储在包括IOMMU的计算机系统的存储器系统中的一个或多个I / O转换表的转换数据。控制逻辑被配置为使用转换数据来转换I / O设备生成的存储器请求。翻译数据包括指示翻译的一个或多个属性的类型字段，并且控制逻辑被配置为响应于类型字段来控制翻译。

66. 发明授权

US07809923B2 Direct memory access (DMA) address translation in an input/output memory management unit (IOMMU) 有权
标题翻译：输入/输出存储器管理单元（IOMMU）中的直接存储器访问（DMA）地址转换
公开(公告)号：US07809923B2
公开(公告)日：2010-10-05
申请号：US12635385
申请日：2009-12-10
申请人： Mark D. Hummel , Geoffrey S. Strongin , Mitchell Alsup , Michael Haertel , Andrew W. Lueck
发明人： Mark D. Hummel , Geoffrey S. Strongin , Mitchell Alsup , Michael Haertel , Andrew W. Lueck
IPC分类号： G06F12/10
CPC分类号： G06F12/1081
摘要： In an embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory configured to store translation data; and control logic coupled to the memory and configured to translate an I/O device-generated memory request using the translation data. The translation data corresponds to one or more device table entries in a device table stored in a memory system of a computer system that includes the IOMMU, wherein the device table entry for a given request is selected by an identifier corresponding to the I/O device that generates the request. The translation data further corresponds to one or more I/O page tables, wherein the selected device table entry for the given request includes a pointer to a set of I/O page tables to be used to translate the given request.
摘要翻译：在一个实施例中，输入/输出（I / O）存储器管理单元（IOMMU）包括被配置为存储转换数据的至少一个存储器; 以及控制逻辑，其耦合到所述存储器并且被配置为使用所述翻译数据来转换I / O设备生成的存储器请求。翻译数据对应于存储在包括IOMMU的计算机系统的存储器系统中的设备表中的一个或多个设备表条目，其中给定请求的设备表条目由对应于I / O设备的标识符选择生成请求。翻译数据还对应于一个或多个I / O页表，其中用于给定请求的所选择的设备表条目包括指向要用于转换给定请求的一组I / O页表的指针。

67. 发明申请

US20100011147A1 Virtualizing an IOMMU 有权
标题翻译：虚拟化IOMMU
公开(公告)号：US20100011147A1
公开(公告)日：2010-01-14
申请号：US12562262
申请日：2009-09-18
申请人： Mark D. Hummel , Andrew W. Lueck , Geoffrey S. Strongin , Mitchell Alsup , Michael Haertel
发明人： Mark D. Hummel , Andrew W. Lueck , Geoffrey S. Strongin , Mitchell Alsup , Michael Haertel
IPC分类号： G06F12/08 , G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45579 , G06F2009/45583
摘要： In one embodiment, a system comprises one or more input/output (I/O) devices; an I/O memory management unit (IOMMU) coupled to receive memory requests sourced by the I/O devices and configured to provide address translation for the memory requests; and a virtual machine monitor (VMM) configured to manage one or more virtual machines on the system, wherein the VMM is configured to virtualize the IOMMU, providing one or more virtual IOMMUs for use by one or more virtual machines.
摘要翻译：在一个实施例中，系统包括一个或多个输入/输出（I / O）设备; I / O存储器管理单元（IOMMU），其耦合以接收由所述I / O设备提供的存储器请求，并被配置为提供所述存储器请求的地址转换; 以及被配置为管理所述系统上的一个或多个虚拟机的虚拟机监视器（VMM），其中所述VMM被配置为虚拟化所述IOMMU，提供一个或多个虚拟IOMMU供一个或多个虚拟机使用。

68. 发明授权

US07631160B2 Method and apparatus for securing portions of memory 有权
公开(公告)号：US07631160B2
公开(公告)日：2009-12-08
申请号：US09825905
申请日：2001-04-04
申请人： Geoffrey S. Strongin , Brian C. Barnes , Rodney Schmidt
发明人： Geoffrey S. Strongin , Brian C. Barnes , Rodney Schmidt
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F11/30 , G06F12/14
CPC分类号： G06F21/79 , G06F12/1483
摘要： The present invention provides a method and apparatus for securing portions of a memory. The method includes identifying information for protection and indicating at least one physical address of a memory that houses the information as at least one of read and write disabled. The method includes receiving a request from a program to access the information. The method further includes accessing the information in response to determining that the program has the authority to access the information. The apparatus includes a memory comprising a privileged code. The privileged code is capable of receiving a request to protect selected information and indicating at least one physical address of a memory housing the information as at least one of read and write disabled. The privileged code is capable of receiving a request from a program to access the information. The privileged code is further capable of accessing the information in response to determining that the program has the authority to access the information.

69. 发明申请

US20090193230A1 COMPUTER SYSTEM INCLUDING A MAIN PROCESSOR AND A BOUND SECURITY COPROCESSOR 审中-公开
标题翻译：包括一个主处理器和一个重要的安全性共同计算机的计算机系统
公开(公告)号：US20090193230A1
公开(公告)日：2009-07-30
申请号：US12022446
申请日：2008-01-30
申请人： Ralf Findeisen , Geoffrey S. Strongin , Andrew R. Rawson , Garth D. Hillman , Gary H. Simpson
发明人： Ralf Findeisen , Geoffrey S. Strongin , Andrew R. Rawson , Garth D. Hillman , Gary H. Simpson
IPC分类号： G06F15/80
CPC分类号： G06F21/74 , G06F21/445 , G06F21/575 , G06F21/71 , G06F2221/2101 , G06F2221/2105
摘要： A computer system includes a main processor and a security control processor that is coupled to the main processor and configured to control and monitor an operational state of the main processor. To ensure the computer system may be trusted, the security control processor may be configured to hold the main processor in a slave mode during initialization of the security control processor such that the main processor is not operable to fetch and execute instructions from an instruction source external to the main processor, for example. In addition, the security control processor may be configured to initialize the operational state of the main processor to a predetermined state by transferring to the main processor via a control interface one or more instructions and to cause the main processor to execute the one or more instructions while the main processor is held in the slave mode.
摘要翻译：计算机系统包括主处理器和安全控制处理器，其连接到主处理器并且被配置为控制和监视主处理器的操作状态。为了确保计算机系统可以被信任，安全控制处理器可以被配置为在安全控制处理器的初始化期间将主处理器保持在从模式，使得主处理器不可操作地从指令源外部获取和执行指令以主处理器为例。此外，安全控制处理器可以被配置为通过经由控制接口将一个或多个指令传送到主处理器来将主处理器的操作状态初始化到预定状态，并且使主处理器执行一个或多个指令而主处理器则保持在从模式。

70. 发明授权

US07493498B1 Input/output permission bitmaps for compartmentalized security 有权
标题翻译：用于区隔安全性的输入/输出权限位图
公开(公告)号：US07493498B1
公开(公告)日：2009-02-17
申请号：US10107784
申请日：2002-03-27
申请人： Rodney W. Schmidt , Brian C. Barnes , Geoffrey S. Strongin
发明人： Rodney W. Schmidt , Brian C. Barnes , Geoffrey S. Strongin
IPC分类号： G06F12/14
CPC分类号： G06F21/52 , G06F12/1483 , G06F12/1491
摘要： A method and apparatus for selectively executing an I/O instruction. The method includes creating an I/O permission bitmap in a memory and receiving an I/O port number and a security context identification (SCID) value. The method also includes using the SCID value and the I/O port number to access the I/O permission bitmap stored to obtain a permission bit corresponding to the I/O port and executing the I/O instruction dependent upon a value of the permission bit corresponding to the I/O port. The I/O permission bitmap includes a plurality of permission bits. Each of the permission bits corresponds to a different one of a plurality of I/O ports. Each of the permission bits has a value indicating whether access to the corresponding I/O port is allowed. The I/O port number indicates the I/O port referenced by the I/O instruction. The SCID value indicates a security context level of a memory location including the I/O instruction.
摘要翻译：一种用于选择性地执行I / O指令的方法和装置。该方法包括在存储器中创建I / O许可位图并接收I / O端口号和安全上下文标识（SCID）值。该方法还包括使用SCID值和I / O端口号来访问存储的I / O许可位图，以获得对应于I / O端口的许可位，并根据许可的值执行I / O指令位对应于I / O端口。 I / O许可位图包括多个许可位。每个许可位对应于多个I / O端口中的不同的一个。每个许可位具有指示是否允许对对应的I / O端口的访问的值。 I / O端口号表示I / O指令引用的I / O端口。 SCID值指示包括I / O指令的存储器位置的安全上下文级别。

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