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61. 发明授权

US5796275A High voltages detector circuit and integrated circuit using same 失效
标题翻译：高电压检测电路和集成电路采用相同方式
公开(公告)号：US5796275A
公开(公告)日：1998-08-18
申请号：US791700
申请日：1997-01-30
申请人： Paolo Rolandi , Massimo Montanaro
发明人： Paolo Rolandi , Massimo Montanaro
IPC分类号： G01R19/165 , H03K17/30 , H03K5/153
CPC分类号： H03K17/302 , G01R19/16519
摘要： The circuit, in accordance with the present invention is for detecting the presence at a signal input of a high voltage higher than a predetermined value and signaling it to a signal output through a logical type signal. The circuit comprises one or more first transistors of MOS type and of a predetermined conductivity type, each being diode-connected and having its body terminal connected to the source terminal, and having principal conduction paths connected in series for current conduction between a first node and a ground input. The circuit also includes two or more second transistors of the MOS type and of the same conductivity type, with each one being diode-connected and having its body terminal connected to the source terminal and having principal conduction paths connected in series for current conduction between the signal input and the first node. At least one first logical inverter of the CMOS type has its input connected to the first node and its output coupled to the signal output and is also connected for power supply to a power supply input and to the ground input.
摘要翻译：根据本发明的电路用于检测在高于预定值的高电压的信号输入处的存在并将其信号通过逻辑类型信号输出的信号。电路包括一个或多个MOS型和预定导电类型的第一晶体管，每个第二晶体管是二极管连接的，其主体端子连接到源极端子，并且具有串联连接的主要导电路径，用于在第一节点和地面输入。该电路还包括两个或更多个MOS型和相同导电类型的第二晶体管，其中每一个二极管连接并且其主体端子连接到源极端子并且具有串联连接的主要导电路径，用于在信号输入和第一个节点。 CMOS型的至少一个第一逻辑逆变器的输入连接到第一节点，其输出耦合到信号输出，并且还被连接用于电源输入和接地输入。

62. 发明授权

US5267202A Reading device for EPROM memory cells with the operational field independent of the threshold jump of the written cells with respect to the virgin cells 失效
标题翻译：用于EPROM存储器单元的读取装置，其操作字段与写入的单元相对于原始单元的阈值跳跃无关
公开(公告)号：US5267202A
公开(公告)日：1993-11-30
申请号：US725987
申请日：1991-07-05
申请人： Marco Dallabora , Paolo Rolandi , Marco Maccalli
发明人： Marco Dallabora , Paolo Rolandi , Marco Maccalli
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28 , G11C11/40
CPC分类号： G11C16/28
摘要： The device comprises a source bias generator suitable for conferring upon the EPROM cell during the reading step a source voltage that varies linearly with the power supply voltage so as to keep constant the voltage between gate and source of the above cell.

63. 发明授权

US08626990B2 Non-volatile configuration for serial non-volatile memory 有权
标题翻译：用于串行非易失性存储器的非易失性配置
公开(公告)号：US08626990B2
公开(公告)日：2014-01-07
申请号：US13143075
申请日：2008-12-30
申请人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
发明人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F9/44573 , G06F2212/72 , G11C16/10 , G11C16/20
摘要： Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device.
摘要翻译：用于配置串行非易失性存储器设备的示例性实施例可以包括用于存储从处理器接收的配置值的非易失性配置寄存器，该配置值指定存储器访问操作的一个或多个属性。至少部分地响应于施加到存储器件的功率来读取配置值。

64. 发明授权

US07397700B2 Non-volatile memory electronic device with NAND structure being monolithically integrated on semiconductor 有权
标题翻译：具有NAND结构的非易失性存储器电子器件单片集成在半导体上
公开(公告)号：US07397700B2
公开(公告)日：2008-07-08
申请号：US11279381
申请日：2006-04-11
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C11/34
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells and with at least one associated row decoding circuit portion. Advantageously, the matrix includes at least one logic sector with pairs of rows or word lines being short-circuited with each other and referring to a respective biasing terminal, one for each pair, and in that the row decoding circuit portion includes a single select block which controls a single multiplexer for the logic sector for the regulation of the signals applied to the biasing terminals.
摘要翻译：非易失性存储器电子器件被集成在半导体上并且是具有NAND类型的架构的闪存EEPROM类型，其包括以行或字线和存储器单元的列或位线组织的至少一个存储器矩阵，并且至少具有一个相关联的行解码电路部分。有利地，矩阵包括至少一个逻辑扇区，其中成对的行或字线彼此短路并且参考相应的偏置端子，每对一个，并且行解码电路部分包括单个选择块其控制用于逻辑扇区的单个多路复用器用于调节施加到偏置端子的信号。

65. 发明申请

US20060227609A1 NON-VOLATILE MEMORY ELECTRONIC DEVICE WITH NAND STRUCTURE BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR 有权
标题翻译：具有NAND结构的非易失性存储器件电子器件单一集成在半导体
公开(公告)号：US20060227609A1
公开(公告)日：2006-10-12
申请号：US11279378
申请日：2006-04-11
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile memory electronic device is integrated on a semiconductor with an architecture including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells. The matrix is divided into at least a first and a second memory portions having a different access speed. The first and second memory portions may share the structures of the bit lines which correspond to one another and one by one and are electrically interrupted by controlled switches placed between the first and the second portions.
摘要翻译：非易失性存储器电子器件集成在具有包括以行或字线和存储器单元的列或位线组织的至少一个存储器矩阵的架构的半导体上。矩阵被分成至少具有不同访问速度的第一和第二存储器部分。第一和第二存储器部分可以共享彼此对应的位线的结构并且逐个地并且被放置在第一和第二部分之间的受控开关电中断。

66. 发明申请

US20060028872A1 Read/verify circuit for multilevel memory cells with ramp read voltage, and read/verify method thereof 有权
标题翻译：具有斜坡读取电压的多电平存储单元的读取/验证电路及其读取/验证方法
公开(公告)号：US20060028872A1
公开(公告)日：2006-02-09
申请号：US11178240
申请日：2005-07-08
申请人： Paolo Rolandi , Luigi Pascucci
发明人： Paolo Rolandi , Luigi Pascucci
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/28 , G11C16/3454 , G11C16/3459 , G11C2211/5634
摘要： A read/verify circuit for multilevel memory cells includes: a read terminal selectively connectable to a plurality of array cells, having respective array threshold voltages; a plurality of reference cells, having respective reference threshold voltages; and a plurality of threshold-detection circuits, for detecting the array thresholds and the reference thresholds. In particular, the read terminal and the reference cells are each connected to a respective threshold-detection circuit. Each threshold-detection circuit is provided with a respective detector element of a resistive type, set so as to be traversed by a current response to turning-on of the respective array cell or reference cell associated thereto.
摘要翻译：用于多电平存储器单元的读/验电路包括：可选择地连接到具有相应阵列阈值电压的多个阵列单元的读终端; 多个参考单元，具有各自的参考阈值电压; 以及用于检测阵列阈值和参考阈值的多个阈值检测电路。特别地，读取终端和参考单元各自连接到相应的阈值检测电路。每个阈值检测电路设置有电阻型的相应检测器元件，其被设置为通过与其相关联的相应阵列单元或参考单元的导通的电流响应来遍历。

67. 发明授权

US06882231B2 Adjustable frequency oscillator with programmable calibrating circuit and related system and method 有权
标题翻译：具有可编程校准电路的可调频振荡器及相关系统及方法
公开(公告)号：US06882231B2
公开(公告)日：2005-04-19
申请号：US10406628
申请日：2003-04-02
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： H03K3/03 , H03L7/00 , H03B27/00
CPC分类号： H03K3/0315 , H03L7/00
摘要： An adjustable frequency oscillator circuit includes: an odd number of inverters connected so as to form a loop; a plurality of capacitive elements each connected to an output terminal of a respective inverter; and an output terminal, which supplies a signal oscillating at an oscillating frequency. The oscillator circuit further includes a calibration circuit for calibrating maximum currents which can be delivered by the inverters to the respective capacitive elements.
摘要翻译：可变频振荡电路包括：奇数个反相器连接成一个环路; 多个电容元件，各自连接到各个逆变器的输出端子; 以及输出端子，其提供以振荡频率振荡的信号。振荡器电路还包括校准电路，用于校准可由反相器传送到各个电容元件的最大电流。

68. 发明申请

US20050068803A1 Method for controlling programming voltage levels of non-volatile memory cells, the method tracking the cell features, and corresponding voltage regulator 有权
公开(公告)号：US20050068803A1
公开(公告)日：2005-03-31
申请号：US10651019
申请日：2003-08-28
申请人： Paolo Rolandi , Luigi Pascucci
发明人： Paolo Rolandi , Luigi Pascucci
IPC分类号： G11C11/00 , G11C11/34 , G11C16/12
CPC分类号： G11C16/12
摘要： A method for controlling programming voltage levels of non-volatile memory cells comprises: providing a resistive divider connected to a programming voltage reference and effective to generate at least one programming voltage level; and providing a reference cell crossed by a cell current. Advantageously according to an embodiment of the invention the cell current is applied to the resistive divider to correlate the programming voltage level to the intrinsic features of the reference cell. A programming voltage regulator of non-volatile memory cells comprises at least an input stage inserted between a first and a second voltage reference and connected to a reference memory cell, as well as, in correspondence with its output terminal, to a resistive divider, inserted in turn between a programming voltage reference and the second voltage reference and connected to at least an output terminal of the regulator, effective to supply the programming voltage to the non-volatile memory cells. Advantageously according to an embodiment of the invention, the output terminal of the input stage is connected to a first circuit node of the resistive divider in correspondence with an end of a resistive element comprised in the resistive divider and having a further end connected to the programming voltage reference. In such a way, a voltage value obtained by shunting the programming voltage reference is applied at the first circuit node. The voltage regulator according to embodiments of the invention can be used in two-level contexts and in multilevel contexts, even for parallel programming of several multilevel memory cells.

69. 发明申请

US20050063236A1 Sense amplifier 有权
标题翻译：感应放大器
公开(公告)号：US20050063236A1
公开(公告)日：2005-03-24
申请号：US10913788
申请日：2004-08-06
申请人： Mauro Pagliato , Massimo Montanaro , Paolo Rolandi
发明人： Mauro Pagliato , Massimo Montanaro , Paolo Rolandi
IPC分类号： G11C7/06 , G11C11/56 , G11C16/28 , G11C11/34
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062 , G11C7/067 , G11C16/28
摘要： A sense amplifier is provided that includes a measure branch receiving an input current to be detected, a reference branch receiving a reference current, equalizing means, and a comparator. The equalizing means selectively equalizes a measure node of the measure branch with a reference node of the reference branch, and the comparator compares a voltage at the measure node of the measure branch with a voltage at the reference node of the reference branch. The equalizing means are such that, when activated, equalization of the measure node with the reference node is virtual and substantially does not involve a flow of current between the measure node and the reference node of the reference branch. The sense amplifier is particularly suited for reading memory cells of a semiconductor memory. Also provided is a method for sensing an input current.
摘要翻译：提供了一种读出放大器，其包括接收待检测的输入电流的测量分支，接收参考电流的参考分支，均衡装置和比较器。均衡装置选择性地将测量分支的测量节点与参考分支的参考节点进行均衡，并且比较器将测量分支的测量节点处的电压与参考分支的参考节点处的电压进行比较。均衡装置使得当激活时，具有参考节点的测量节点的均衡是虚拟的并且基本上不涉及测量节点和参考分支的参考节点之间的电流。读出放大器特别适用于读取半导体存储器的存储单元。还提供了用于感测输入电流的方法。

70. 发明授权

US06683808B2 String programmable nonvolatile memory with NOR architecture 有权
标题翻译：具有NOR架构的字符串可编程非易失性存储器
公开(公告)号：US06683808B2
公开(公告)日：2004-01-27
申请号：US10179553
申请日：2002-06-24
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C8/10
摘要： A nonvolatile memory having a NOR architecture has a memory array including a plurality of memory cells arranged in rows and columns in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines; and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.
摘要翻译：具有NOR结构的非易失性存储器具有存储器阵列，其包括以NOR形状排列成行和列的多个存储单元，布置在同一列上的存储单元连接到多个位线之一; 和列解码器。列解码器包括多个选择级，每个选择级连接到相应的位线并且接收第一位线寻址信号。选择级包括由第一位线寻址信号控制的字编程选择器，并将编程电压提供给每个选择级的仅一位位线。每个选择级还包括由第二位线寻址信号控制的串编程选择电路，从而同时将编程电压提供给每个选择级的多个位线。

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