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    • 66. 发明授权
    • Trench-capacitor DRAM device and manufacture method thereof
    • 沟槽电容器DRAM器件及其制造方法
    • US07332392B2
    • 2008-02-19
    • US11279254
    • 2006-04-11
    • Yung-Chang LinSun-Chieh ChienChien-Li KuoRuey-Chyr Lee
    • Yung-Chang LinSun-Chieh ChienChien-Li KuoRuey-Chyr Lee
    • H01L21/8242
    • H01L29/945H01L27/1087H01L29/66181
    • A trench capacitor structure includes a semiconductor substrate comprising thereon a STI structure. A capacitor deep trench is etched into the semiconductor substrate. Collar oxide layer is disposed on inner surface of the capacitor deep trench. A first doped polysilicon layer is disposed on the collar oxide layer and on the exposed bottom of the capacitor deep trench. A capacitor dielectric layer is formed on the first doped polysilicon layer. A second doped polysilicon layer is formed on the capacitor dielectric layer. A deep ion well is formed in the semiconductor substrate, wherein the deep ion well is electrically connected with the first doped polysilicon layer through the bottom of the capacitor deep trench. A passing gate insulation (PGI) layer is formed on the second doped polysilicon layer and on the STI structure.
    • 沟槽电容器结构包括其上包括STI结构的半导体衬底。 电容器深沟槽被蚀刻到半导体衬底中。 环状氧化物层设置在电容器深沟槽的内表面上。 第一掺杂多晶硅层设置在轴环氧化物层和电容器深沟槽的暴露的底部上。 在第一掺杂多晶硅层上形成电容器电介质层。 第二掺杂多晶硅层形成在电容器介电层上。 在半导体衬底中形成深离子阱,其中深离子阱通过电容器深沟槽的底部与第一掺杂多晶硅层电连接。 在第二掺杂多晶硅层和STI结构上形成通过栅极绝缘(PGI)层。