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61. 发明授权

US08907316B2 Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions 有权
标题翻译：具有与多晶和单晶半导体区域的pn结的存储单元访问装置
公开(公告)号：US08907316B2
公开(公告)日：2014-12-09
申请号：US12267453
申请日：2008-11-07
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Yen-Hao Shih , Yi-Chou Chen , Shih-Hung Chen
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Yen-Hao Shih , Yi-Chou Chen , Shih-Hung Chen
IPC分类号： H01L47/00 , H01L45/00 , H01L27/102 , H01L27/24 , H01L29/861 , H01L29/165 , H01L29/04 , G11C13/00
CPC分类号： H01L29/8616 , G11C13/0004 , G11C2213/72 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L29/04 , H01L29/165 , H01L29/861 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675 , H01L45/1683
摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions.
摘要翻译：存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体区域，第一和第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区形成在单晶半导体中，并且所述第二掺杂半导体区包括多晶半导体。此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与所述第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定所述第一和第二区域之间的pn结。

62. 发明授权

US08664689B2 Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions 有权
标题翻译：具有与多晶硅插头和单晶半导体区域的pn结的存储单元访问装置
公开(公告)号：US08664689B2
公开(公告)日：2014-03-04
申请号：US12267492
申请日：2008-11-07
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Yen-Hao Shih , Yi-Chou Chen , Shih-Hung Chen
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Yen-Hao Shih , Yi-Chou Chen , Shih-Hung Chen
IPC分类号： H01L29/861 , H01L29/88
CPC分类号： H01L45/1233 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L29/861 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675 , H01L45/1683
摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.
摘要翻译：存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体插头，第一和第第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区域形成在单晶半导体中，并且所述第二掺杂半导体区域包括多晶半导体。此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定第一和第二区域之间的pn结。

63. 发明授权

US08581327B2 Memory and manufacturing method thereof 有权
公开(公告)号：US08581327B2
公开(公告)日：2013-11-12
申请号：US12974093
申请日：2010-12-21
申请人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
发明人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/66545 , H01L29/66583 , H01L29/7923
摘要： A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.

64. 发明申请

US20110089480A1 MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：内存及其制造方法
公开(公告)号：US20110089480A1
公开(公告)日：2011-04-21
申请号：US12974093
申请日：2010-12-21
申请人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
发明人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/66545 , H01L29/66583 , H01L29/7923
摘要： A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.
摘要翻译：提供具有隔离双存储单元的存储器。第一隔离壁和第二隔离壁分别设置在基板上的源极和漏极之间。隔离底层和多晶硅层有序地设置在第一和第二隔离壁之间的衬底上。第一电荷存储结构和第一栅极有序地设置在第一隔离壁和源极之间的衬底上。第二电荷存储结构和第二栅极有序地设置在第二隔离壁和漏极之间的衬底上。布置在多晶硅层上的字线，第一栅极，第二栅极，第一隔离壁和第二隔离壁电连接到第一栅极，第二栅极和多晶硅层。

65. 发明授权

US07704865B2 Methods of forming charge-trapping dielectric layers for semiconductor memory devices 有权
标题翻译：形成用于半导体存储器件的电荷俘获介电层的方法
公开(公告)号：US07704865B2
公开(公告)日：2010-04-27
申请号：US11209875
申请日：2005-08-23
申请人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/425
CPC分类号： H01L21/2652 , H01L21/28211 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/7923
摘要： Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.
摘要翻译：在半导体存储器件中形成电荷俘获电介质层结构的方法包括：（a）提供半导体衬底; （b）在所述基材的至少一部分上形成氧化物层; （c）在氧化物层下面的衬底中形成两个或更多个源极/漏极区域; （d）氧化氧化层; （e）在所述氧化物层上形成电荷捕获电介质层; 和（f）在电荷俘获电介质层上形成绝缘层; 以及包括：（a）提供半导体衬底的方法; （b）在干燥气氛中在所述基材的至少一部分上形成氧化物层; （c）在氧化物层下面的衬底中形成两个或更多个源极/漏极区域; （d）在氧化物层上形成电荷俘获介电层; （e）在电荷捕获介电层上形成绝缘层; 和（f）在氢含量小于约0.01％的气氛中退火绝缘层。

66. 发明申请

US20090140321A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090140321A1
公开(公告)日：2009-06-04
申请号：US11949090
申请日：2007-12-03
申请人： Erh-Kun Lai , Yen-Hao Shih
发明人： Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L29/792 , H01L21/283
CPC分类号： H01L27/11573 , H01L21/3144
摘要： A semiconductor device and a method of fabricating the same are provided. First, a first oxide layer and a nitride layer are formed on a base having a first region and a second region. Next, the nitride layer is oxidized. A part of nitride in the nitride layer moves to the first oxide layer and the base. An upper portion of the nitride layer is converted to an upper oxide layer. Then, the upper oxide layer, the nitride layer and the first oxide layer in the second region are removed. Thereon, a second oxide layer is grown on the base in the second region. Nitride in the second region moves to the second oxide layer.
摘要翻译：提供半导体器件及其制造方法。首先，在具有第一区域和第二区域的基底上形成第一氧化物层和氮化物层。接下来，氮化物层被氧化。氮化物层中的氮化物的一部分移动到第一氧化物层和基底。氮化物层的上部被转换为上部氧化物层。然后，除去第二区域中的上氧化物层，氮化物层和第一氧化物层。其次，在第二区域的基底上生长第二氧化物层。第二区域中的氮化物移动到第二氧化物层。

67. 发明申请

US20070281423A1 Method for manufacuring semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070281423A1
公开(公告)日：2007-12-06
申请号：US11445870
申请日：2006-06-02
申请人： Yen-Hao Shih , Erh-Kun Lai
发明人： Yen-Hao Shih , Erh-Kun Lai
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11546 , H01L27/11568 , H01L29/78
摘要： A method for manufacturing a plurality of memory devices and a plurality of high voltage devices on a substrate are provided. The substrate has a memory region and a high voltage region. The method comprises steps of forming a first dielectric layer on the substrate and then performing a thermal process so as to enlarge the thickness of the first dielectric layer in the high voltage region. A buried diffusion region is formed in the substrate in the memory region and a charge trapping layer and a blocking dielectric layer are formed over the substrate in the memory region. A patterned conductive layer is formed over the substrate so as to form gates the memory region and the high voltage region respectively and then a source/drain region is formed adjacent to the gates in the high voltage region in the substrate.
摘要翻译：提供了一种用于在基板上制造多个存储器件和多个高电压器件的方法。衬底具有存储区和高电压区。该方法包括以下步骤：在衬底上形成第一电介质层，然后进行热处理，以扩大高电压区域中的第一电介质层的厚度。在存储区中的衬底中形成掩埋扩散区，并且在存储区中的衬底上形成电荷俘获层和阻挡电介质层。在衬底上形成图案化的导电层，以分别形成存储区域和高电压区域的栅极，然后在衬底中的高电压区域中邻近栅极形成源极/漏极区域。

68. 发明申请

US20060292800A1 ONO formation of semiconductor memory device and method of fabricating the same 有权
标题翻译： ONO形成半导体存储器件及其制造方法
公开(公告)号：US20060292800A1
公开(公告)日：2006-12-28
申请号：US11159269
申请日：2005-06-23
申请人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833
摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.
摘要翻译：一种制造非易失性存储器件的方法至少包括以下步骤。首先，提供形成有底部电介质层的基板。然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。该结构被热退火以推动间隔开的掺杂区域向外扩散。退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

69. 发明申请

US20140042629A1 SEMICONDUCTING MULTI-LAYER STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体多层结构及其制造方法
公开(公告)号：US20140042629A1
公开(公告)日：2014-02-13
申请号：US13584366
申请日：2012-08-13
申请人： Erh-Kun Lai , Yen-Hao Shih
发明人： Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L23/485 , H01L21/28
CPC分类号： H01L27/11582 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each of the first insulating layers covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the two lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.
摘要翻译：公开了一种包括多个第一导电层，多个第一绝缘层和第二导电层的半导体多层结构。第一导电层分开设置。每个第一导电层具有上表面，与上表面相对的底表面和侧表面。第一绝缘层围绕第一导电层的外围设备。每个第一绝缘层覆盖每个第一导电层的上表面的至少一部分，每个第一导电层的每个的底表面的至少一部分和每个第一导电层的两个侧表面。第二导电层覆盖第一导电层和第一绝缘层。

70. 发明授权

US07754545B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07754545B2
公开(公告)日：2010-07-13
申请号：US11949090
申请日：2007-12-03
申请人： Erh-Kun Lai , Yen-Hao Shih
发明人： Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L21/339 , H01L21/84
CPC分类号： H01L27/11573 , H01L21/3144
摘要： A semiconductor device and a method of fabricating the same are provided. First, a first oxide layer and a nitride layer are formed on a base having a first region and a second region. Next, the nitride layer is oxidized. A part of nitride in the nitride layer moves to the first oxide layer and the base. An upper portion of the nitride layer is converted to an upper oxide layer. Then, the upper oxide layer, the nitride layer and the first oxide layer in the second region are removed. Thereon, a second oxide layer is grown on the base in the second region. Nitride in the second region moves to the second oxide layer.
摘要翻译：提供半导体器件及其制造方法。首先，在具有第一区域和第二区域的基底上形成第一氧化物层和氮化物层。接下来，氮化物层被氧化。氮化物层中的氮化物的一部分移动到第一氧化物层和基底。氮化物层的上部被转换为上部氧化物层。然后，除去第二区域中的上氧化物层，氮化物层和第一氧化物层。其次，在第二区域的基底上生长第二氧化物层。第二区域中的氮化物移动到第二氧化物层。

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