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61. 发明授权

US06538276B2 Split gate flash memory device with shrunken cell and source line array dimensions 有权
标题翻译：具有缩小单元和源极线阵列尺寸的分离式闪存器件
公开(公告)号：US06538276B2
公开(公告)日：2003-03-25
申请号：US09755281
申请日：2001-01-08
申请人： Chia-Ta Hsieh , Yai-Fen Liu , Hung-Cheng Sung , Di-Son Kuo
发明人： Chia-Ta Hsieh , Yai-Fen Liu , Hung-Cheng Sung , Di-Son Kuo
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Form intermetal dielectric and control gate layers over the substrate covering the stack and the source regions and the drain regions. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Pattern a source line slot in the center of the gate electrode stack down to the substrate. Form source regions through the source line slot. Form drain regions self-aligned with the split gate electrodes and the gate electrode stack.
摘要翻译：形成分离栅电极MOSFET器件的方法包括以下步骤。在半导体衬底上形成隧道氧化层。在隧道氧化物层上形成浮栅电极层。在浮栅电极层上形成掩蔽帽。以掩模盖的图案形成由隧道氧化物层和浮栅电极层形成的栅电极堆叠。在覆盖堆叠和源极区域和漏极区域的衬底上方形成金属间电介质和控制栅极层。将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。将栅极电极堆叠的中心的源极线槽图案化为衬底。通过源线槽形成源区。形成漏极区域与分离栅电极和栅极电极堆叠自对准。

62. 发明授权

US06245685B1 Method for forming a square oxide structure or a square floating gate structure without rounding effect 有权
标题翻译：用于形成方形氧化物结构的方法或不具有圆角效应的方形浮栅结构
公开(公告)号：US06245685B1
公开(公告)日：2001-06-12
申请号：US09387441
申请日：1999-09-01
申请人： Hung-Cheng Sung , Di-Son Kuo , Chia-Ta Hsieh
发明人： Hung-Cheng Sung , Di-Son Kuo , Chia-Ta Hsieh
IPC分类号： H01L2100
CPC分类号： H01L27/11521 , H01L21/28114 , H01L21/28123 , H01L21/31144 , H01L21/32 , H01L21/823842 , H01L27/115
摘要： A method for forming a square oxide structure or a square floating gate without a rounding effect at its corners. A first dielectric layer is formed on a pad layer for a square oxide structure or a polysilicon layer overlying a gate oxide layer for a floating gate, and a second dielectric layer is formed on the first dielectric layer. The second dielectric layer is patterned to form parallel openings in a first direction using a first photosensitive mask. A second photosensitive mask, having a plurality of parallel openings in a second direction perpendicular to the first direction is formed over the second dielectric layer and the first dielectric layer. The first dielectric layer is etched through square openings where the openings in the second photosensitive mask and the openings in the second dielectric layer intersect, thereby forming square openings in the first dielectric layer. The second photosensitive mask and the second dielectric layer are removed. The square oxide structure is completed by etching a trench in the semiconductor structure and forming an STI or LOCOS. The square floating gate is completed by growing polysilicon oxide structures in the square openings in the first dielectric layer and removing the first dielectric layer to form a pattern of openings therebetween, and etching the polysilicon layer through the pattern of openings between the polysilicon oxide structures forming square floating gate polysilicon regions under the polysilicon oxide hard masks.
摘要翻译：用于在其角部形成平方氧化物结构或方形浮动栅极而不具有圆化效应的方法。第一电介质层形成在用于平面氧化物结构的焊盘层或覆盖用于浮置栅极的栅极氧化物层的多晶硅层上，并且第二介电层形成在第一介电层上。图案化第二电介质层以使用第一感光掩模在第一方向上形成平行的开口。在第二电介质层和第一电介质层上形成第二光敏掩模，在与第一方向垂直的第二方向上具有多个平行的开口。通过正方形开口蚀刻第一电介质层，其中第二感光掩模中的开口和第二介电层中的开口相交，从而在第一介电层中形成方形开口。去除第二光敏掩模和第二介电层。通过蚀刻半导体结构中的沟槽并形成STI或LOCOS来完成平方氧化物结构。通过在第一电介质层的正方形开口中生长多晶氧化物结构并去除第一电介质层以形成其间的开口图案来完成正方形浮栅，并且通过形成多晶硅氧化物结构之间的开口图案蚀刻多晶硅层方形浮栅多晶硅区域下的多晶硅氧化物硬掩模。

63. 发明授权

US06284596B1 Method of forming split-gate flash cell for salicide and self-align contact 有权
标题翻译：形成用于自对准和自对准接触的裂开闪光单元的方法
公开(公告)号：US06284596B1
公开(公告)日：2001-09-04
申请号：US09213453
申请日：1998-12-17
申请人： Hung-Cheng Sung , Di-Son Kuo , Chia-Ta Hsieh
发明人： Hung-Cheng Sung , Di-Son Kuo , Chia-Ta Hsieh
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned. Hence, with this method, salicidation and self-aligned contact techniques can be used not only on the same VLSI and ULSI chips having both peripheral logic devices and memory devices, but also in memory devices themselves.
摘要翻译：公开了一种用于形成具有盐化控制栅极和自对准触点的分离栅极闪存单元的方法。通常用单栅极器件（例如逻辑器件）执行致敏。在分支栅极中，其中控制栅极与中间栅极氧化物层覆盖浮置栅极，因为它们的位置与浮置栅极的位置处于不同的水平位置，因此在控制栅极上形成自对准硅化物是常规的不相容的。此外，通常使用的氧化物间隔物在应用于存储单元时是不充分的。在本发明中显示，通过在控制栅极上明智地使用另外的氮化物/氧化物层，现在可以有效地使用氧化物间隔物来描绘控制栅上可被硅化并且自对准的区域。因此，利用这种方法，不仅可以使用具有外围逻辑器件和存储器件的同一VLSI和ULSI芯片，而且可以用于存储器件本身中，可以使用水化和自对准接触技术。

64. 发明授权

US06559501B2 Method for forming split-gate flash cell for salicide and self-align contact 有权
标题翻译：用于形成用于自对准和自对准接触的裂开闪光单元的方法
公开(公告)号：US06559501B2
公开(公告)日：2003-05-06
申请号：US09850639
申请日：2001-05-07
申请人： Hung-Cheng Sung , Di-Son Kuo , Chia-Ta Hsieh
发明人： Hung-Cheng Sung , Di-Son Kuo , Chia-Ta Hsieh
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned. Hence, with this method, salicidation and self-aligned contact techniques can be used not only on the same VLSI and ULSI chips having both peripheral logic devices and memory devices, but also in memory devices themselves.
摘要翻译：公开了一种用于形成具有盐化控制栅极和自对准触点的分离栅极闪存单元的方法。通常用单栅极器件（例如逻辑器件）执行致敏。在分支栅极中，其中控制栅极与中间栅极氧化物层覆盖浮置栅极，因为它们的位置与浮置栅极的位置处于不同的水平位置，因此在控制栅极上形成自对准硅化物是常规的不相容的。此外，通常使用的氧化物间隔物在应用于存储单元时是不充分的。在本发明中显示，通过在控制栅极上明智地使用另外的氮化物/氧化物层，现在可以有效地使用氧化物间隔物来描绘控制栅上可被硅化并且自对准的区域。因此，利用这种方法，不仅可以使用具有外围逻辑器件和存储器件的同一VLSI和ULSI芯片，而且可以用于存储器件本身中，可以使用水化和自对准接触技术。

65. 发明申请

US20050156224A1 Method to make minimal spacing between floating gates in split gate flash 审中-公开
公开(公告)号：US20050156224A1
公开(公告)日：2005-07-21
申请号：US11059987
申请日：2005-02-17
申请人： Chia-Ta Hsieh , Yi-Jiun Lin , Feng-Jia Shiu , Hung-Cheng Sung , Chi-Hsin Lo
发明人： Chia-Ta Hsieh , Yi-Jiun Lin , Feng-Jia Shiu , Hung-Cheng Sung , Chi-Hsin Lo
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.

66. 发明授权

US06569736B1 Method for fabricating square polysilicon spacers for a split gate flash memory device by multi-step polysilicon etch 有权
标题翻译：通过多步多晶硅蚀刻制造用于分离栅极闪存器件的方形多晶硅间隔物的方法
公开(公告)号：US06569736B1
公开(公告)日：2003-05-27
申请号：US10076668
申请日：2002-02-14
申请人： Cheng-Yuan Hsu , Hung-Cheng Sung , Su-Chang Chen , Han-Ping Chen , Chia-Ta Hsieh , Der-Shin Shyu
发明人： Cheng-Yuan Hsu , Hung-Cheng Sung , Su-Chang Chen , Han-Ping Chen , Chia-Ta Hsieh , Der-Shin Shyu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/6656 , H01L29/66825
摘要： A method for forming square polysilicon spacers on a split gate flash memory device by a multi-step polysilicon etch process is described. The method can be carried out by depositing a polysilicon layer on the flash memory device structure and then depositing a sacrificial layer, such as silicon oxide, on top of the polysilicon layer. The sacrificial layer has a slower etch rate than the polysilicon layer during a main etch step. The sacrificial layer overlies the flash memory device is then removed, while the sacrificial layer on the sidewall is kept intact. The polysilicon layer that overlies the flash memory device is then etched away followed by a step of removing all residual sacrificial layers. The exposed polysilicon layer is then etched to define the square polysilicon spacers on the split gate flash memory device.
摘要翻译：描述了通过多步多晶硅蚀刻工艺在分裂栅极闪存器件上形成方形多晶硅间隔物的方法。该方法可以通过在闪存器件结构上沉积多晶硅层，然后在多晶硅层的顶部上沉积牺牲层，例如氧化硅来进行。在主蚀刻步骤期间，牺牲层具有比多晶硅层更慢的蚀刻速率。覆盖闪存器件的牺牲层然后被去除，同时侧壁上的牺牲层保持完整。然后将覆盖在闪速存储器件上的多晶硅层蚀刻掉，随后除去所有残余牺牲层的步骤。然后蚀刻暴露的多晶硅层以在分裂栅极闪存器件上限定方形多晶硅间隔物。

67. 发明申请

US20060046403A1 Method of forming separated charge-holding regions in a semiconductor device 审中-公开
标题翻译：在半导体器件中形成分离的电荷保持区域的方法
公开(公告)号：US20060046403A1
公开(公告)日：2006-03-02
申请号：US10931547
申请日：2004-08-31
申请人： Wen-Ting Chu , Chia-Ta Hsieh , Hung-Cheng Sung
发明人： Wen-Ting Chu , Chia-Ta Hsieh , Hung-Cheng Sung
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3205
CPC分类号： H01L29/512 , H01L21/28202 , H01L29/40117 , H01L29/518 , H01L29/66833
摘要： A method of forming a semiconductor device comprises forming a gate dielectric layer and a gate electrode over the gate dielectric layer on a semiconductor substrate, partially removing the gate dielectric layer to form two recesses separated by the gate dielectric layer and disposed substantially under the gate electrode, and substantially filling the two recesses with an oxide layer and a material layer to form two separated regions operable to each hold an electrical charge.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上的栅介电层上形成栅极电介质层和栅电极，部分地去除栅极电介质层以形成由栅极电介质层分开并设置在栅电极下方的两个凹槽并且用氧化物层和材料层基本上填充两个凹部以形成可操作以保持电荷的两个分离的区域。

68. 发明授权

US06881629B2 Method to make minimal spacing between floating gates in split gate flash 失效
标题翻译：在分闸门闪存中使浮栅之间的间距最小的方法
公开(公告)号：US06881629B2
公开(公告)日：2005-04-19
申请号：US10655662
申请日：2003-09-05
申请人： Chia-Ta Hsieh , Yi-Jiun Lin , Feng-Jia Shiu , Hung-Cheng Sung , Chi-Hsin Lo
发明人： Chia-Ta Hsieh , Yi-Jiun Lin , Feng-Jia Shiu , Hung-Cheng Sung , Chi-Hsin Lo
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01I21/8247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.
摘要翻译：实现了在集成电路器件中形成MOS栅极的新方法。该方法对于在分离栅极闪存晶体管中形成浮置栅极特别有用。该方法包括提供基底。在衬底上形成介电层。形成覆盖在电介质层上的导体层。第一掩模层沉积在导体层上。图案化第一掩模层以选择性地暴露导体层。第二掩模层沉积在第一掩模层和导体层上。第二掩模层被回蚀刻以在第一掩模层的侧壁上形成间隔物。通过第一掩模层和间隔物露出的导体层被蚀刻，从而在集成电路器件的制造中形成MOS栅极。

69. 发明申请

US20050054162A1 METHOD TO MAKE MINIMAL SPACING BETWEEN FLOATING GATES IN SPLIT GATE FLASH 失效
标题翻译：在分流闸闪存中浮动门之间产生最小间距的方法
公开(公告)号：US20050054162A1
公开(公告)日：2005-03-10
申请号：US10655662
申请日：2003-09-05
申请人： Chia-Ta Hsieh , Yi-Jiun Lin , Feng-Jia Shiu , Hung-Cheng Sung , Chi-Hsin Lo
发明人： Chia-Ta Hsieh , Yi-Jiun Lin , Feng-Jia Shiu , Hung-Cheng Sung , Chi-Hsin Lo
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.
摘要翻译：实现了在集成电路器件中形成MOS栅极的新方法。该方法对于在分离栅极闪存晶体管中形成浮置栅极特别有用。该方法包括提供基底。在衬底上形成介电层。形成覆盖在电介质层上的导体层。第一掩模层沉积在导体层上。图案化第一掩模层以选择性地暴露导体层。第二掩模层沉积在第一掩模层和导体层上。第二掩模层被回蚀刻以在第一掩模层的侧壁上形成间隔物。通过第一掩模层和间隔物露出的导体层被蚀刻，从而在集成电路器件的制造中形成MOS栅极。

70. 发明授权

US06251744B1 Implant method to improve characteristics of high voltage isolation and high voltage breakdown 有权
标题翻译：植入法提高高压隔离和高压击穿特性
公开(公告)号：US06251744B1
公开(公告)日：2001-06-26
申请号：US09356870
申请日：1999-07-19
申请人： Hung-Der Su , Chrong-Jung Lin , Jong Chen , Wen-Ting Chu , Hung-Cheng Sung , Di-Son Kuo
发明人： Hung-Der Su , Chrong-Jung Lin , Jong Chen , Wen-Ting Chu , Hung-Cheng Sung , Di-Son Kuo
IPC分类号： H01L2176
CPC分类号： H01L21/76213
摘要： A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.
摘要翻译：在半导体衬底的n阱或p阱区域上生长一层良好的氧化物。在高电压器件区域中进行深n阱注入，随后是深n阱注入的深n阱驱动。去除氧化物; 在高电压器件区域中产生场氧化物（FOX）区域。牺牲氧化物层沉积在半导体衬底的表面上。在半导体衬底的高电压PMOS区域中执行低电压簇n阱注入，随后是高压NMOS区，由低电压簇p阱注入，随后是埋置的p阱簇注入。

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