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61. 发明申请

US20090013299A1 BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS 审中-公开
标题翻译：缓冲插入减少VLSI电路中的WIRELENGTH
公开(公告)号：US20090013299A1
公开(公告)日：2009-01-08
申请号：US12207498
申请日：2008-09-10
申请人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F2217/84
摘要： Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
摘要翻译：集成电路设计网络中的线长通过形成要互连的接收集群，在每个集群中插入缓冲区并通过将一个集群的接收器连接到另一个集群的缓冲区来提供集群之间的分支连接来减少，以创建一个跨越所有水槽的缓冲树。缓冲区被插入到最靠近网络源的簇的相应边界框上的点处。提供与另一个群集的缓冲区的分支连接的宿是与该缓冲区最接近的宿（除了群集中的那些宿）。可以通过用不同的边界框检查不同对的汇，并且将其边界框中具有最小半周的对中的一个作为聚类的最佳对来形成群集。

62. 发明申请

US20070271543A1 Buffer Insertion to Reduce Wirelength in VLSI Circuits 有权
标题翻译：缓冲插入以减少VLSI电路中的线长度
公开(公告)号：US20070271543A1
公开(公告)日：2007-11-22
申请号：US11383544
申请日：2006-05-16
申请人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F2217/84
摘要： Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
摘要翻译：集成电路设计网络中的线长通过形成要互连的接收集群，在每个集群中插入缓冲区并通过将一个集群的接收器连接到另一个集群的缓冲区来提供集群之间的分支连接来减少，以创建一个跨越所有水槽的缓冲树。缓冲区被插入到最靠近网络源的簇的相应边界框上的点处。提供与另一个群集的缓冲区的分支连接的宿是与该缓冲区最接近的宿（除了群集中的那些宿）。可以通过用不同的边界框检查不同对的汇，并且将其边界框中具有最小半周的对中的一个作为聚类的最佳对来形成群集。

63. 发明授权

US07484199B2 Buffer insertion to reduce wirelength in VLSI circuits 有权
标题翻译：缓冲器插入以减少VLSI电路中的电线长度
公开(公告)号：US07484199B2
公开(公告)日：2009-01-27
申请号：US11383544
申请日：2006-05-16
申请人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
发明人： Charles J. Alpert , Tuhin Mahmud , Stephen T. Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F2217/84
摘要： Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
摘要翻译：集成电路设计网络中的线长通过形成要互连的接收集群，在每个集群中插入缓冲区并通过将一个集群的接收器连接到另一个集群的缓冲区来提供集群之间的分支连接来减少，以创建一个跨越所有水槽的缓冲树。缓冲区被插入到最靠近网络源的簇的相应边界框上的点处。提供与另一个群集的缓冲区的分支连接的宿是与该缓冲区最接近的宿（除了群集中的那些宿）。可以通过用不同的边界框检查不同对的汇，并且将其边界框中具有最小半周的对中的一个作为聚类的最佳对来形成群集。

64. 发明申请

US20070283301A1 System and Method of Eliminating Electrical Violations 审中-公开
标题翻译：消除电气违规的制度和方法
公开(公告)号：US20070283301A1
公开(公告)日：2007-12-06
申请号：US11422174
申请日：2006-06-05
申请人： Arvind K. Karandikar , Charles J. Alpert , Mehmet C. Yildiz , Stephen T. Quay , Tuhin Mahmud , Paul G. Villarrubia
发明人： Arvind K. Karandikar , Charles J. Alpert , Mehmet C. Yildiz , Stephen T. Quay , Tuhin Mahmud , Paul G. Villarrubia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081 , G06F17/5045
摘要： A system and method for correcting electrical violations, the method including examining a plurality of nets for at least one electrical violation in a sequential order of a first output-to-input traversal, and determining a net correction in each net of the plurality of nets having an electrical violation prior to examining a next net in the sequential order of the first output-to-input traversal.
摘要翻译：一种用于校正电气违规的系统和方法，所述方法包括以第一输出到输入遍历的顺序检查多个网络中的至少一个电气违规，以及确定多个网络的每个网络中的净校正在按照第一输出到输入遍历的顺序检查下一个网络之前具有电气违规。

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