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61. 发明授权

US07271069B2 Semiconductor device having a plurality of different layers and method therefor 有权
标题翻译：具有多个不同层的半导体器件及其方法
公开(公告)号：US07271069B2
公开(公告)日：2007-09-18
申请号：US11111451
申请日：2005-04-21
申请人： Marius K. Orlowski , Vance H. Adams
发明人： Marius K. Orlowski , Vance H. Adams
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/78 , H01L29/7846 , H01L29/7848
摘要： Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.
摘要翻译：可以使用具有选定的弹性模量的材料实现机械应力控制。这些材料可以通过注入选择性地形成，可以设置为插入在基板和有源区域之间的多个掩埋层，并且可以通过替换一个或多个掩埋层的选定部分来形成。这些方法中的任何一种或多种可以组合使用。机械应力控制在半导体器件的通道区域中可能是有用的，以使其性能最大化。此外，除了机械应力控制之外，这些相同的技术和结构可以用于其它目的。

62. 发明授权

US07256077B2 Method for removing a semiconductor layer 失效
标题翻译：去除半导体层的方法
公开(公告)号：US07256077B2
公开(公告)日：2007-08-14
申请号：US10851607
申请日：2004-05-21
申请人： Marius K. Orlowski
发明人： Marius K. Orlowski
IPC分类号： H01L21/84
CPC分类号： H01L29/78639 , H01L29/42392 , H01L29/66772
摘要： A method of forming a semiconductor device includes forming a first layer over a semiconductor substrate and forming a second layer over the first layer. The second layer includes silicon and has an etch selectivity to the second layer that is greater than approximately 1,000. In one embodiment, the second layer is a porous material, such as porous silicon, porous silicon germanium, porous silicon carbide, and porous silicon carbon alloy. A gate insulator is formed over the second layer and a control electrode is formed over the gate insulator. The first layer is selectively removed with respect to the second layer and the semiconductor substrate.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成第一层并在第一层上形成第二层。第二层包括硅，并且对第二层具有大于约1,000的蚀刻选择性。在一个实施方案中，第二层是多孔材料，例如多孔硅，多孔硅锗，多孔碳化硅和多孔硅碳合金。在第二层上形成栅极绝缘体，并且在栅极绝缘体上形成控制电极。相对于第二层和半导体衬底选择性地去除第一层。

63. 发明授权

US07238555B2 Single transistor memory cell with reduced programming voltages 有权
标题翻译：具有降低编程电压的单晶体管存储单元
公开(公告)号：US07238555B2
公开(公告)日：2007-07-03
申请号：US11172570
申请日：2005-06-30
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/108 , G11C16/0408 , H01L27/10802 , H01L29/7841
摘要： A transistor fabrication method includes forming an electrode overlying a channel of a semiconductor on insulator (SOI) substrate. Source/drain structures are formed in the substrate on either side of the channel. The source/drain structures include a layer of a second semiconductor over a first semiconductor. The first and second semiconductors have different bandgaps. The second semiconductor extends under the gate electrode. The source/drain structures may be formed by doping the source/drain regions and etching the doped regions selectively to form voids. A film of the second semiconductor is then grown epitaxially to fill the void. A film of the first semiconductor may be grown to line the void before growing the second semiconductor. Alternatively, the second semiconductor is a continuous layer that extends through the channel body. A capping layer of the first semiconductor may lie over the second semiconductor in this embodiment.
摘要翻译：晶体管制造方法包括形成覆盖绝缘体上半导体（SOI）衬底的沟道的电极。源极/漏极结构形成在沟道两侧的衬底中。源极/漏极结构包括在第一半导体上的第二半导体层。第一和第二半导体具有不同的带隙。第二半导体在栅电极下延伸。源极/漏极结构可以通过掺杂源极/漏极区域并且选择性地蚀刻掺杂区域以形成空隙来形成。然后第二半导体的膜外延生长以填充空隙。可以在生长第二半导体之前，使第一半导体的膜生长以排列空隙。或者，第二半导体是延伸穿过通道体的连续层。在该实施例中，第一半导体的覆盖层可以位于第二半导体上。

64. 发明授权

US07205202B2 Semiconductor device and method for regional stress control 有权
标题翻译：用于区域应力控制的半导体器件和方法
公开(公告)号：US07205202B2
公开(公告)日：2007-04-17
申请号：US11111450
申请日：2005-04-21
申请人： Marius K. Orlowski , Vance H. Adams
发明人： Marius K. Orlowski , Vance H. Adams
IPC分类号： H01L21/331
CPC分类号： H01L27/1203 , H01L21/84 , H01L21/86 , H01L29/7846
摘要： Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.
摘要翻译：可以使用具有选定的弹性模量的材料实现机械应力控制。这些材料可以通过注入选择性地形成，可以设置为插入在基板和有源区域之间的多个掩埋层，并且可以通过替换一个或多个掩埋层的选定部分来形成。这些方法中的任何一种或多种可以组合使用。机械应力控制在半导体器件的通道区域中可能是有用的，以使其性能最大化。此外，除了机械应力控制之外，这些相同的技术和结构可以用于其它目的。

65. 发明授权

US07195963B2 Method for making a semiconductor structure using silicon germanium 有权
标题翻译：使用硅锗制造半导体结构的方法
公开(公告)号：US07195963B2
公开(公告)日：2007-03-27
申请号：US10851347
申请日：2004-05-21
申请人： Marius K. Orlowski , Chun-Li Liu , Choh-Fei Yeap
发明人： Marius K. Orlowski , Chun-Li Liu , Choh-Fei Yeap
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/1033 , H01L29/66628 , H01L29/66742 , H01L29/66772 , H01L29/7834 , H01L29/78606 , H01L29/78639 , H01L29/78687
摘要： Silicon carbon is used as a diffusion barrier to germanium so that a silicon layer can be subsequently formed without being contaminated with germanium. This is useful in separating silicon layers from silicon germanium layers in situations in which both silicon and silicon germanium are desired to be present on the same semiconductor device such as for providing different materials for optimizing carrier mobility between N and P channel transistors and for a raised source/drain of silicon in the case of a silicon germanium body.
摘要翻译：硅碳被用作锗的扩散阻挡层，从而可以随后形成硅层而不被锗污染。这在硅硅层分离的同时，硅和硅锗希望存在于同一半导体器件上，例如为了提供不同的材料以优化N沟道晶体管和P沟道晶体管之间的载流子迁移率，在硅锗体的情况下硅的源极/漏极。

66. 发明授权

US07135379B2 Isolation trench perimeter implant for threshold voltage control 有权
公开(公告)号：US07135379B2
公开(公告)日：2006-11-14
申请号：US10955658
申请日：2004-09-30
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76237
摘要： A method of forming isolation trenches in a semiconductor fabrication process to reduce transistor channel edge effect currents includes forming a masking structure overlying a substrate to expose a first area of the substrate. Spacers are formed on sidewalls of the masking structure. The spacers cover a perimeter region of the first area thereby leaving a second smaller area exposed. The region underlying the second area is etched to form an isolation trench that is then filled with a dielectric. The spacers are removed to expose the perimeter region. Using the masking structure and the trench dielectric as a mask, an impurity distribution is implanted into a portion of the substrate underlying the perimeter region. The impurity distribution thus surrounds a perimeter of the trench dielectric proximal to an upper surface of the substrate. The perimeter impurity distribution dopant, in a typical case, is p-type for NMOS transistors and n-type for PMOS.

67. 发明授权

US07112832B2 Transistor having multiple channels 有权
标题翻译：具有多个通道的晶体管
公开(公告)号：US07112832B2
公开(公告)日：2006-09-26
申请号：US11091980
申请日：2005-03-29
申请人： Marius K. Orlowski , Leo Mathew
发明人： Marius K. Orlowski , Leo Mathew
IPC分类号： H01L29/80
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66772 , H01L29/66795 , H01L29/78654
摘要： A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled to source and drain electrodes (S/D) to provide increased channel surface area in a same area that a single channel structure is conventionally implemented. A vertical channel dimension between two regions of the gate (60) are controlled by a growth process as opposed to lithographical or spacer formation techniques. The gate is adjacent all sides of the multiple overlying channels. Each channel is formed by growth from a common seed layer and the source and drain electrodes and the channels are formed of a substantially homogenous crystal lattice.
摘要翻译：晶体管（10）覆盖在衬底（12）上并且具有以堆叠布置形成的多个覆盖通道（72,74,76）。连续的门（60）材料围绕每个通道。每个通道耦合到源极和漏极（S / D），以在通常实现单通道结构的相同区域中提供增加的沟道表面积。栅极（60）的两个区域之间的垂直沟道尺寸由生长过程控制，而不是光刻或间隔物形成技术。门与多个上覆通道的所有侧相邻。每个通道由普通种子层生长形成，源极和漏极以及通道由基本均匀的晶格形成。

68. 发明授权

US07037795B1 Low RC product transistors in SOI semiconductor process 有权
标题翻译： SOI半导体工艺中的低RC产品晶体管
公开(公告)号：US07037795B1
公开(公告)日：2006-05-02
申请号：US10965964
申请日：2004-10-15
申请人： Alexander L. Barr , Olubunmi O. Adetutu , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
发明人： Alexander L. Barr , Olubunmi O. Adetutu , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/78618
摘要： A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.
摘要翻译：半导体制造工艺包括在半导体衬底上的掩埋氧化物层（BOX）上形成半导体顶层的SOI晶片的晶体管栅极。设置在栅极两侧的源极/漏极沟槽被蚀刻到BOX层中。源极/漏极结构形成在沟槽内。源极/漏极结构的深度大于顶部硅层的厚度，并且源极/漏极结构的上表面大致与晶体管沟道重合，源极/漏极结构与栅极之间的垂直重叠可忽略不计。沟槽优选地延伸穿过BOX层以暴露硅衬底的一部分。源极/漏极结构优选外延地形成，并且可能包括富氧阶段和无氧阶段的两个阶段。两个外延级之间的热退火将在源极/漏极结构和衬底之间形成隔离电介质。

69. 发明授权

US06964911B2 Method for forming a semiconductor device having isolation regions 有权
标题翻译：用于形成具有隔离区域的半导体器件的方法
公开(公告)号：US06964911B2
公开(公告)日：2005-11-15
申请号：US10668714
申请日：2003-09-23
申请人： Marius K. Orlowski , Alexander L. Barr
发明人： Marius K. Orlowski , Alexander L. Barr
IPC分类号： H01L21/336 , H01L21/762 , H01L29/78 , H01L21/76
CPC分类号： H01L29/66628 , H01L21/76235 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device having isolation structures decreases leakage current. A channel isolation structure decreases leakage current through a channel structure. In addition, current electrode dielectric insulation structures are formed under current electrode regions to prevent leakage between the current electrodes.
摘要翻译：用于形成具有隔离结构的半导体器件的方法降低了漏电流。通道隔离结构通过沟道结构减少漏电流。此外，在电流电极区域形成电流电极介质绝缘结构，以防止电流电极之间的泄漏。

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