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61. 发明申请

US20080237751A1 CMOS Structure and method of manufacturing same 审中-公开
标题翻译： CMOS结构及其制造方法
公开(公告)号：US20080237751A1
公开(公告)日：2008-10-02
申请号：US11731163
申请日：2007-03-30
申请人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Willy Rachmady
发明人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Willy Rachmady
IPC分类号： H01L21/8238
CPC分类号： H01L21/82385 , H01L29/785
摘要： A CMOS structure includes a substrate (110, 310), an electrically insulating layer (120, 320) over the substrate, NMOS (130, 330) and PMOS (140, 340) semiconducting structures over the electrically insulating layer, and a dielectric layer (150, 350) having first (151, 351) and second (152, 352) portions over, respectively, the NMOS and PMOS semiconducting structures. The NMOS and PMOS semiconducting structures have, respectively, a first height (135, 335) and a second height (145, 345). The CMOS structure further includes a first electrically conducting layer (160, 360) over the first portion of the dielectric layer, a second electrically conducting layer (170, 370) over the second portion of the dielectric layer and thicker than the first electrically conducting layer, a first polysilicon layer (180, 780) over the first electrically conducting layer, and a second polysilicon layer (190, 790) over the second electrically conducting layer and thinner than the first polysilicon layer.
摘要翻译： CMOS结构包括衬底（110,310），衬底上的电绝缘层（120,320），电绝缘层上的NMOS（130,330）和PMOS（140,340）半导体结构，以及介电层（150,350）分别在NMOS和PMOS半导体结构之上具有第一（151,351）和第二（152,352）部分。 NMOS和PMOS半导体结构分别具有第一高度（135,335）和第二高度（145,345）。 CMOS结构还包括位于电介质层的第一部分上的第一导电层（160,360），在介电层的第二部分上方的第二导电层（170,370），并且比第一导电层，在所述第一导电层上方的第一多晶硅层（180,780）以及所述第二导电层上的第二多晶硅层（190,790）并且比所述第一多晶硅层更薄。

62. 发明申请

US20080157225A1 SRAM and logic transistors with variable height multi-gate transistor architecture 审中-公开
标题翻译：具有可变高度多栅极晶体管结构的SRAM和逻辑晶体管
公开(公告)号：US20080157225A1
公开(公告)日：2008-07-03
申请号：US11648521
申请日：2006-12-29
申请人： Suman Datta , Brian S. Doyle , Jack T. Kavalieros , Yih Wang
发明人： Suman Datta , Brian S. Doyle , Jack T. Kavalieros , Yih Wang
IPC分类号： H01L21/336 , H01L29/768
CPC分类号： H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/66795 , H01L29/7851
摘要： Multi-gate transistors having different channel widths formed on non-planar semiconductor bodies have different sidewall heights and method of manufacturing the same. In an embodiment, a multi-gate SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a multi-gate logic transistor to improve performance of SRAM and logic transistors formed on the same substrate. In another embodiment, to reduce cell area, a first SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a second multi-gate SRAM transistor.
摘要翻译：形成在非平面半导体主体上的具有不同沟道宽度的多栅极晶体管具有不同的侧壁高度及其制造方法。在一个实施例中，多栅极SRAM晶体管形成在具有比用于多栅极逻辑晶体管的非平面半导体主体更大的侧壁高度的非平面半导体主体上，以改善在栅极上形成的SRAM和逻辑晶体管的性能相同的底物。在另一个实施例中，为了减小单元面积，第一SRAM晶体管形成在具有比用于第二多栅极SRAM晶体管的非平面半导体主体更大的侧壁高度的非平面半导体本体上。

63. 发明申请

US20080003755A1 Sacrificial oxide layer which enables spacer over-etch in tri-gate architectures 审中-公开
标题翻译：牺牲氧化物层，其在三栅结构中实现间隔体过蚀刻
公开(公告)号：US20080003755A1
公开(公告)日：2008-01-03
申请号：US11479713
申请日：2006-06-30
申请人： Uday Shah , Willy Rachmady , Jack T. Kavalieros , Brian S. Doyle
发明人： Uday Shah , Willy Rachmady , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/66795 , H01L29/7851
摘要： Embodiments of methods and apparatus for a sacrificial oxide layer which enables spacer over-etch in multi-gate architectures are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述了能够在多门体系结构中实现间隔物过蚀刻的牺牲氧化物层的方法和装置的实施例。可以描述和要求保护其他实施例。

64. 发明授权

US06972225B2 integrating n-type and P-type metal gate transistors 有权
标题翻译：集成n型和P型金属栅极晶体管
公开(公告)号：US06972225B2
公开(公告)日：2005-12-06
申请号：US10946502
申请日：2004-09-20
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
摘要翻译：至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

65. 发明授权

US06858483B2 Integrating n-type and p-type metal gate transistors 有权
标题翻译：集成n型和p型金属栅晶体管
公开(公告)号：US06858483B2
公开(公告)日：2005-02-22
申请号：US10327293
申请日：2002-12-20
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
摘要翻译：至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

66. 发明申请

US20100163945A1 Embedded memory cell and method of manufacturing same 有权
标题翻译：嵌入式存储单元及其制造方法
公开(公告)号：US20100163945A1
公开(公告)日：2010-07-01
申请号：US12319101
申请日：2008-12-30
申请人： Jack T. Kavalieros , Niloy Mukherjee , Gilbert Dewey , Dinesh Somasekhar , Brian S. Doyle
发明人： Jack T. Kavalieros , Niloy Mukherjee , Gilbert Dewey , Dinesh Somasekhar , Brian S. Doyle
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10832 , H01L27/10861 , H01L27/10867 , H01L27/1087 , H01L27/10876 , H01L28/90 , H01L29/66666 , H01L29/7827
摘要： An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.
摘要翻译：嵌入式存储单元包括半导体衬底（110），具有至少部分地嵌入在半导体衬底中的源极/漏极区域（121）的晶体管（120）以及至少部分地嵌入在半导体衬底中的电容器（130）。电容器包括通过第一电绝缘材料（133）彼此电绝缘的第一电极（131）和第二电极（132）。第一电极电连接到半导体衬底，第二电极电连接到晶体管的源极/漏极区域。

67. 发明授权

US07629643B2 Independent n-tips for multi-gate transistors 有权
标题翻译：多栅极晶体管的独立n尖端
公开(公告)号：US07629643B2
公开(公告)日：2009-12-08
申请号：US11948414
申请日：2007-11-30
申请人： Ravi Pillarisetty , Suman Datta , Jack T. Kavalieros , Brian S. Doyle
发明人： Ravi Pillarisetty , Suman Datta , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L27/108
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11 , H01L29/785
摘要： Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices, and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device.
摘要翻译：通常描述多栅极晶体管的独立n尖端。在一个示例中，设备包括半导体鳍片，与半导体鳍片耦合的一个或多个多栅极下拉（PD）器件，所述一个或多个PD器件在与半导体鳍片材料相邻的半导体鳍片材料中具有n尖端掺杂剂浓度一个或多个PD器件，以及与半导体鳍片耦合的一个或多个多栅极通过栅极（PG）器件，所述一个或多个PG器件在与所述一个或多个PG相邻的半导体鳍片材料中具有n尖端掺杂剂浓度器件，其中PG器件的n尖掺杂剂浓度低于PD器件的n尖掺杂剂浓度。

68. 发明申请

US20090166742A1 REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY INCORPORATION OF A PARTIAL METALLIC FIN 有权
标题翻译：通过加入部分金属粉末来降低多门装置的外部电阻
公开(公告)号：US20090166742A1
公开(公告)日：2009-07-02
申请号：US11964623
申请日：2007-12-26
申请人： Ravi Pillarisetty , Uday Shah , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
发明人： Ravi Pillarisetty , Uday Shah , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L29/94 , H01L21/8234
CPC分类号： H01L29/785 , H01L29/66795
摘要： Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.
摘要翻译：通常描述通过结合部分金属翅片来降低多栅极器件的外部电阻。在一个示例中，设备包括半导体衬底和与半导体衬底耦合的多栅极晶体管器件的一个或多个鳍片，该一个或多个鳍片具有栅极区域，源极区域和漏极区域，栅极区域设置在源极和漏极区域之间，其中一个或多个鳍片的栅极区域包括半导体材料，并且其中一个或多个鳍片的源极和漏极区域包括金属部分和半导体部分，金属部分和半导体部分联接在一起。

69. 发明申请

US20090166741A1 REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES 有权
标题翻译：使用间隔加工技术降低多门装置的外部电阻
公开(公告)号：US20090166741A1
公开(公告)日：2009-07-02
申请号：US11964593
申请日：2007-12-26
申请人： Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
发明人： Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/785
摘要： Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.
摘要翻译：通常描述使用间隔物处理技术降低多栅极器件的外部电阻。在一个示例中，一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上，一个或多个多栅极鳍片包括栅极区域，源极区域和漏极区域，栅极区域设置在源极和漏极区域，图案化牺牲栅极电极，使得牺牲栅电极材料耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到一个或多个多栅极鳍片的源极和漏极区域，形成电介质薄膜耦合到一个或多个多栅极鳍片的源极和漏极区域，从一个或多个多栅极鳍片的栅极区域去除牺牲栅电极，将间隔栅极电介质沉积到该一个或多个多栅极散热片的栅极区域多栅极翅片，其中基本上没有间隔栅极电介质沉积到一个或多个多栅极鳍片的源极和漏极区域，源极和漏极区域被电介质fi 并且蚀刻间隔栅极电介质，以将栅极区域的栅极区域完全去除以与最终栅电极耦合的间隔栅极电介质，除了要与保持耦合的最终栅电极耦合的间隔栅极电介质的剩余预定厚度与电介质膜。

70. 发明申请

US20090061611A1 FABRICATING DUAL LAYER GATE ELECTRODES HAVING POLYSILICON AND A WORKFUNCTION METAL 审中-公开
标题翻译：制造具有多晶硅和工作金属的双层门电极
公开(公告)号：US20090061611A1
公开(公告)日：2009-03-05
申请号：US11848239
申请日：2007-08-30
申请人： Willy Rachmady , Uday Shah , Jack T. Kavalieros , Brian S. Doyle
发明人： Willy Rachmady , Uday Shah , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L21/3205
CPC分类号： H01L29/4958 , H01L21/28079 , H01L21/28088 , H01L29/66795 , H01L29/785
摘要： A method for fabricating a dual layer gate electrode having a polysilicon layer and a workfunction metal layer comprises depositing a layer of a workfunction metal on a semiconductor substrate, depositing a layer of polysilicon on the workfunction metal layer, depositing a hard mask layer on the polysilicon layer, etching the hard mask layer to form a hard mask structure defining a gate electrode, etching the polysilicon layer to remove a portion of the polysilicon layer not protected by the hard mask structure, thereby forming a polysilicon structure beneath the hard mask structure, applying a mixture of ozone and water to exposed sidewalls of the polysilicon structure, thereby forming a silicon dioxide layer on the sidewalls, and etching the workfunction metal layer to remove a portion of the workfunction metal layer not protected by the hard mask structure, thereby forming a workfunction metal structure beneath the polysilicon structure.
摘要翻译：一种用于制造具有多晶硅层和功函数金属层的双层栅电极的方法，包括在半导体衬底上沉积功函数金属层，在功函数金属层上沉积多晶硅层，在多晶硅上沉积硬掩模层蚀刻硬掩模层以形成限定栅电极的硬掩模结构，蚀刻多晶硅层以去除未被硬掩模结构保护的多晶硅层的一部分，从而在硬掩模结构下方形成多晶硅结构，施加将臭氧和水的混合物混合到多晶硅结构的暴露的侧壁，从而在侧壁上形成二氧化硅层，并蚀刻功函数金属层以除去未被硬掩模结构保护的功能金属层的一部分，从而形成多晶硅结构下面的功函数金属结构。

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