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61. 发明申请

US20070096218A1 EEPROM ARRAY WITH WELL CONTACTS 有权
标题翻译： EEPROM阵列与良好的联系
公开(公告)号：US20070096218A1
公开(公告)日：2007-05-03
申请号：US11567805
申请日：2006-12-07
申请人： Atsuhiro Sato , Kikuko Sugimae , Masayuki Ichige
发明人： Atsuhiro Sato , Kikuko Sugimae , Masayuki Ichige
IPC分类号： H01L29/94
CPC分类号： H01L27/11519 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell well contact area. The layout pattern of the second wiring bodies is the same as the layout pattern of the first wiring bodies. The cell well contact area comprises cell well contacts that have the same dopant type as the cell well and that function as source/drain regions of dummy transistors formed in the cell well contact area.
摘要翻译：一种半导体集成电路器件，包括：单元阱，形成在单元阱上的存储单元阵列，具有存储单元区域和单元阱接触区域，布置在存储单元区域中的第一布线体以及布置在单元阱中的第二布线体接触面积第二布线体的布局图案与第一布线体的布局图形相同。电池阱接触区域包括具有与电池阱相同的掺杂剂类型的电池阱触点，并且用作在电池阱接触区域中形成的虚拟晶体管的源极/漏极区域。

62. 发明授权

US07183615B2 Nonvolatile semiconductor memory and manufacturing method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US07183615B2
公开(公告)日：2007-02-27
申请号：US10868773
申请日：2004-06-17
申请人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
发明人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L27/115 , H01L29/42324 , Y10T428/24256
摘要： A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.
摘要翻译：半导体存储器具有存储单元阵列，其包括（a）沿着列方向延伸的器件隔离膜，交替地布置在沿着行方向排列的存储单元晶体管之间，（b）沿行和列方向排列的第一导电层第一导电层的顶表面位于比器件隔离膜的顶表面更低的水平面上，（c）布置在器件隔离膜和第一导电层上的电极间电介质，使得电极间电介质可以由属于不同单元列的存储单元晶体管所共用，电极间电介质的相对介电常数高于器件隔离膜的相对介电常数，（d）沿着行方向延伸的第二导电层，在电极间电介质上。这里，器件隔离膜的上角被倒角。

63. 发明申请

US20060097307A1 Nonvolatile semiconductor memory and manufacturing method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US20060097307A1
公开(公告)日：2006-05-11
申请号：US11311262
申请日：2005-12-20
申请人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
发明人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.
摘要翻译：存储单元晶体管具有第一单元位置栅绝缘体，第一单元位栅极绝缘体上的第一下导电层，第一下导电层上的第一电极间电介质，以及第一电极上的第一上导电层电介质。选择晶体管具有与第一单元位置栅绝缘体相同厚度的第二单元位栅极绝缘体，第二单元位栅极绝缘体上的第二下导电层，第二下导电层上的第二电极间电介质，以及在第二电极间电介质上的第二上导电层。外围晶体管具有第一外围栅极绝缘体，该第一外围栅极绝缘体具有比第一栅极绝缘体更薄的厚度。

64. 发明授权

US07012295B2 Semiconductor memory with peripheral transistors having gate insulator thickness being thinner than thickness of memory and select transistors 失效
标题翻译：具有栅极绝缘体厚度的外围晶体管的半导体存储器比存储器和选择晶体管的厚度更薄
公开(公告)号：US07012295B2
公开(公告)日：2006-03-14
申请号：US10878372
申请日：2004-06-29
申请人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
发明人： Atsuhiro Sato , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.
摘要翻译：存储单元晶体管具有第一单元位置栅绝缘体，第一单元位栅极绝缘体上的第一下导电层，第一下导电层上的第一电极间电介质，以及第一电极上的第一上导电层电介质。选择晶体管具有与第一单元位置栅绝缘体相同厚度的第二单元位栅极绝缘体，第二单元位栅极绝缘体上的第二下导电层，第二下导电层上的第二电极间电介质，以及在第二电极间电介质上的第二上导电层。外围晶体管具有第一外围栅极绝缘体，该第一外围栅极绝缘体具有比第一栅极绝缘体更薄的厚度。

65. 发明申请

US20050105336A1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20050105336A1
公开(公告)日：2005-05-19
申请号：US10944940
申请日：2004-09-21
申请人： Atsuhiro Sato , Yasuhiko Matsunaga , Fumitaka Arai
发明人： Atsuhiro Sato , Yasuhiko Matsunaga , Fumitaka Arai
IPC分类号： G11C16/06 , G11C11/34 , G11C16/04 , G11C16/12 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/12 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： A semiconductor memory includes a memory cell array having a memory cell units, configured from memory cell transistors connected in a column, which have a first and a second control gate disposed on both sides of a floating gate horizontally arranged with a first end connected to a bit line via a first select-gate transistor, and a second end connected to a source line via a second select-gate transistor. The first and the second control gate of memory cell transistors arranged in the same row are connected in common to a first and a second control gate line in a row, respectively. It also includes a boosting circuit, which generates a write-in voltage, multilevel intermediate voltages, and a bit line voltage from a power source, and a row decoder supplied with the write-in voltage and the multilevel intermediate voltages to select the first and the second control gate.
摘要翻译：半导体存储器包括具有存储单元单元的存储单元阵列，存储单元单元由连接在列中的存储单元晶体管构成，其具有设置在浮置栅极两侧的第一和第二控制栅极，水平布置，第一端连接到经由第一选择栅晶体管的位线，以及经由第二选择栅极晶体管连接到源极线的第二端。布置在同一行中的存储单元晶体管的第一和第二控制栅极分别连接到一行中的第一和第二控制栅极线。它还包括升压电路，其从电源产生写入电压，多电平中间电压和位线电压，以及提供有写入电压和多电平中间电压的行解码器，以选择第一和第二控制门。

66. 发明申请

US20050045966A1 Nonvolatile semiconductor memory and manufacturing method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US20050045966A1
公开(公告)日：2005-03-03
申请号：US10868773
申请日：2004-06-17
申请人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
发明人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
IPC分类号： H01L21/76 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/82 , H01L29/76
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L27/115 , H01L29/42324 , Y10T428/24256
摘要： A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.
摘要翻译：半导体存储器具有存储单元阵列，其包括（a）沿着列方向延伸的器件隔离膜，交替地布置在沿着行方向排列的存储单元晶体管之间，（b）沿行和列方向排列的第一导电层第一导电层的顶表面位于比器件隔离膜的顶表面更低的水平面上，（c）布置在器件隔离膜和第一导电层上的电极间电介质，使得电极间电介质可以由属于不同单元列的存储单元晶体管所共用，电极间电介质的相对介电常数高于器件隔离膜的相对介电常数，（d）沿着行方向延伸的第二导电层，在电极间电介质上。这里，器件隔离膜的上角被倒角。

67. 发明授权

US08581325B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08581325B2
公开(公告)日：2013-11-12
申请号：US13412802
申请日：2012-03-06
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/764 , H01L27/11521 , H01L29/42336 , H01L29/66825
摘要： This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the substrate along a first direction and a second direction orthogonal to the first direction, a plurality of charge accumulation layers formed on the tunnel insulator films, respectively, a plurality of element isolation regions formed on the substrate, the element isolation regions including a plurality of trenches formed along the first direction between the tunnel insulator films, a plurality of element isolation films filled in the trenches, a plurality of inter-poly insulator films formed over the element isolation regions and on the upper and side surfaces of the charge accumulation layers along the second direction in a stripe shape, a plurality of air gaps formed between the element isolation films filled in the trenches and the inter-poly insulator films and a plurality of control gate electrodes formed on the inter-poly insulator films.
摘要翻译：该半导体存储器件包括半导体衬底，沿着第一方向和与第一方向正交的第二方向形成在衬底上的多个隧道绝缘膜，分别形成在隧道绝缘膜上的多个电荷累积层，多个形成在衬底上的元件隔离区域，元件隔离区域包括在隧道绝缘膜之间沿着第一方向形成的多个沟槽，填充在沟槽中的多个元件隔离膜，多个多晶硅绝缘膜，形成在多个绝缘膜之上所述元件隔离区域和沿着所述第二方向的所述电荷累积层的上表面和所述侧表面处于条形状，在填充在所述沟槽中的元件隔离膜和所述多晶硅绝缘膜之间形成的多个气隙和多个的多晶硅绝缘膜上形成的控制栅电极。

68. 发明申请

US20120217567A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120217567A1
公开(公告)日：2012-08-30
申请号：US13412802
申请日：2012-03-06
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/764 , H01L27/11521 , H01L29/42336 , H01L29/66825
摘要： This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the substrate along a first direction and a second direction orthogonal to the first direction, a plurality of charge accumulation layers formed on the tunnel insulator films, respectively, a plurality of element isolation regions formed on the substrate, the element isolation regions including a plurality of trenches formed along the first direction between the tunnel insulator films, a plurality of element isolation films filled in the trenches, a plurality of inter-poly insulator films formed over the element isolation regions and on the upper and side surfaces of the charge accumulation layers along the second direction in a stripe shape, a plurality of air gaps formed between the element isolation films filled in the trenches and the inter-poly insulator films and a plurality of control gate electrodes formed on the inter-poly insulator films.
摘要翻译：该半导体存储器件包括半导体衬底，沿着第一方向和与第一方向正交的第二方向形成在衬底上的多个隧道绝缘膜，分别形成在隧道绝缘膜上的多个电荷累积层，多个形成在衬底上的元件隔离区域，元件隔离区域包括在隧道绝缘膜之间沿着第一方向形成的多个沟槽，填充在沟槽中的多个元件隔离膜，多个多晶硅绝缘膜，形成在多个绝缘膜之上所述元件隔离区域和沿着所述第二方向的所述电荷累积层的上表面和所述侧表面处于条形状，在填充在所述沟槽中的元件隔离膜和所述多晶硅绝缘膜之间形成的多个气隙和多个的多晶硅绝缘膜上形成的控制栅电极。

69. 发明授权

US08158479B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08158479B2
公开(公告)日：2012-04-17
申请号：US13211394
申请日：2011-08-17
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/764 , H01L27/11521 , H01L29/42336 , H01L29/66825
摘要： This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the semiconductor substrate along a first direction and a second direction orthogonal to the first direction with certain spaces in each directions, a plurality of charge accumulation layers formed on the plurality of tunnel insulator films, respectively, a plurality of element isolation regions formed on the semiconductor substrate, the plurality of element isolation regions including a plurality of trenches formed along the first direction between the plurality of tunnel insulator films, a plurality of element isolation films filled in the plurality of trenches, a plurality of inter poly insulator films formed over the plurality of element isolation regions and on the upper surface and side surfaces of the plurality of charge accumulation layer along the second direction in a stripe shape, a plurality of air gaps formed between the plurality of element isolation films filled in the plurality of trenches and the plurality of inter poly insulator films and a plurality of control gate electrodes formed on the plurality of inter poly insulator films.
摘要翻译：该半导体存储器件包括半导体衬底，沿着第一方向形成在半导体衬底上的多个隧道绝缘膜，和在每个方向上具有一定间隔的与第一方向正交的第二方向，多个电荷累积层形成在多个分别形成在所述半导体衬底上的多个元件隔离区域，所述多个元件隔离区域包括在所述多个隧道绝缘膜之间沿着所述第一方向形成的多个沟槽，多个元件隔离膜填充在所述多个沟槽中，形成在所述多个元件隔离区域上并且沿着所述第二方向的所述多个电荷蓄积层的上表面和侧表面处于条形状的多个多晶硅绝缘膜，多个气隙形成在多个元件隔离膜之间填充在所述多个沟槽和所述多个多晶硅绝缘膜中，以及形成在所述多个多晶硅绝缘膜上的多个控制栅电极。

70. 发明申请

US20110300703A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110300703A1
公开(公告)日：2011-12-08
申请号：US13211394
申请日：2011-08-17
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L21/28
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/764 , H01L27/11521 , H01L29/42336 , H01L29/66825
摘要： This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the semiconductor substrate along a first direction and a second direction orthogonal to the first direction with certain spaces in each directions, a plurality of charge accumulation layers formed on the plurality of tunnel insulator films, respectively, a plurality of element isolation regions formed on the semiconductor substrate, the plurality of element isolation regions including a plurality of trenches formed along the first direction between the plurality of tunnel insulator films, a plurality of element isolation films filled in the plurality of trenches, a plurality of inter poly insulator films formed over the plurality of element isolation regions and on the upper surface and side surfaces of the plurality of charge accumulation layer along the second direction in a stripe shape, a plurality of air gaps formed between the plurality of element isolation films filled in the plurality of trenches and the plurality of inter poly insulator films and a plurality of control gate electrodes formed on the plurality of inter poly insulator films.
摘要翻译：该半导体存储器件包括半导体衬底，沿着第一方向形成在半导体衬底上的多个隧道绝缘膜，和在每个方向上具有一定间隔的与第一方向正交的第二方向，多个电荷累积层形成在多个分别形成在所述半导体衬底上的多个元件隔离区域，所述多个元件隔离区域包括在所述多个隧道绝缘膜之间沿着所述第一方向形成的多个沟槽，多个元件隔离膜填充在所述多个沟槽中，形成在所述多个元件隔离区域上并且沿着所述第二方向的所述多个电荷蓄积层的上表面和侧表面处于条形状的多个多晶硅绝缘膜，多个气隙形成在多个元件隔离膜之间填充在所述多个沟槽和所述多个多晶硅绝缘膜中，以及形成在所述多个多晶硅绝缘膜上的多个控制栅电极。

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