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    • 61. 发明申请
    • Method And Apparatus For Buffering Streaming Media
    • 缓冲流媒体的方法和装置
    • US20070283035A1
    • 2007-12-06
    • US11766320
    • 2007-06-21
    • Qi Wang
    • Qi Wang
    • G06F15/16
    • H04L65/604H04L47/10H04L47/2416H04L47/25H04L47/266H04L47/30H04L65/80H04N7/17318H04N21/2401H04N21/4307H04N21/4392H04N21/44004
    • Embodiments of the present invention disclose a method for buffering streaming media, including: determining whether there is no free buffer chunk to buffering streaming media currently in a playing buffer; if so, stopping downloading streaming media from the network; otherwise, buffering the streaming media downloaded from the network in the playing buffer; determining whether the time for playing the streaming media after being buffered in the playing buffer is later than the time for playing the steaming media according to the playing speed; if so, stopping playing streaming media in the buffer chunk; otherwise, playing streaming media in the buffer chunk. In accordance with the present invention, the problem of covering streaming media not being played in playing buffer and playing streaming media disconnectedly caused by the difference between the speed of downloading and playing streaming media is avoided by respectively controlling the process of downloading and playing streaming media. In view of the above, it is possible to guarantee that no error occurs in the process of buffering and playing streaming media, and ensure the quality for playing streaming media. Embodiments of the present invention further disclose an apparatus for buffering streaming media.
    • 本发明的实施例公开了一种用于缓冲流媒体的方法,包括:确定是否没有空闲缓冲区块缓冲当前在播放缓冲器中的流媒体; 如果是,请停止从网络下载流媒体; 否则,缓冲在播放缓冲器中从网络下载的流媒体; 确定在播放缓冲器中缓冲后播放流媒体的时间是否比根据播放速度播放蒸汽媒体的时间晚; 如果是这样,停止在缓冲区块中播放流媒体; 否则,在缓冲区块中播放流媒体。 根据本发明,通过分别控制下载和播放流媒体的处理来避免覆盖播放缓冲器中播放的流媒体和播放流媒体间的不兼容的流媒体问题, 。 鉴于上述情况,可以保证在缓冲和播放流媒体的过程中不会发生错误,并确保播放流媒体的质量。 本发明的实施例还公开了一种用于缓冲流媒体的装置。
    • 62. 发明申请
    • Semiconductor structures formed on substrates and methods of manufacturing the same
    • 在基板上形成的半导体结构及其制造方法
    • US20070020884A1
    • 2007-01-25
    • US11189163
    • 2005-07-25
    • Qi WangMinhua LiJeffrey Rice
    • Qi WangMinhua LiJeffrey Rice
    • H01L21/30H01L21/46
    • H01L21/76251H01L21/2007H01L21/6835H01L2221/68368
    • Processes used to transfer semiconductor structures from an initial substrate to a base substrate include bonding the initial substrate with a silicon dioxide layer to a doped silicon structure weakened sufficiently by hydrogen implantation for cleaving. After cleaving, a doped silicon layer remains, burying the silicon dioxide layer between the doped silicon layer and the initial substrate. Semiconductor structures are formed within/on an epitaxial layer disposed on the doped silicon layer forming an intermediate semiconductor structure. A process handle is temporarily bonded to the semiconductor structures for support. The initial substrate is thinned and removed by a mechanical thinning process followed by chemical etching using the buried silicon dioxide layer as an etch stop. The silicon dioxide layer is chemically removed from the doped silicon layer. A base substrate is formed on the doped silicon layer. The process handle is removed leaving the semiconductor structures disposed on the base substrate.
    • 用于将半导体结构从初始衬底转移到基底衬底的工艺包括将初始衬底与二氧化硅层结合到通过氢注入充分削弱的用于裂解的掺杂硅结构。 在分裂之后,保留掺杂的硅层,将二氧化硅层埋在掺杂硅层和初始衬底之间。 半导体结构形成在设置在掺杂硅层上的外延层内/之上,形成中间半导体结构。 工艺手柄临时粘合到用于支撑的半导体结构。 通过机械稀化处理使初始底物变薄并除去,然后使用掩埋二氧化硅层作为蚀刻停止层进行化学蚀刻。 从掺杂硅层化学去除二氧化硅层。 基底衬底形成在掺杂硅层上。 去除处理手柄,留下设置在基底基板上的半导体结构。
    • 63. 发明申请
    • Power Trench MOSFETs Having SiGe/Si Channel Structure
    • 具有SiGe / Si通道结构的功率沟槽MOSFET
    • US20060289916A1
    • 2006-12-28
    • US11469456
    • 2006-08-31
    • Chanho ParkQi Wang
    • Chanho ParkQi Wang
    • H01L27/108H01L31/00
    • H01L29/7813H01L29/1054H01L29/165H01L29/49H01L29/4933H01L29/66734H01L29/7782Y02P70/605
    • Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Other device characteristics are also improved. For example, parasitic gate impedance can reduced through the use of a poly SiGe gate. Also, channel resistance can be reduced through the use of a SiGe layer near the device's gate and a thick oxide region can be formed under the trench gate to reduce gate-to-drain capacitance.
    • 提高对瞬态电压的抗扰度并减少寄生阻抗的器件,方法和过程。 提高对松开感应开关事件的抗扰度。 例如,提供了具有SiGe源的沟槽门控功率MOSFET器件,其中SiGe源通过减少主体或阱区中的空穴电流来降低寄生npn晶体管增益,从而降低闩锁状态的可能性。 还提供了具有SiGe体或阱区的沟槽栅功率MOSFET器件。 当体二极管导通时,SiGe体减小空穴电流,从而降低反向恢复功率损耗。 其他装置特性也得到改善。 例如,通过使用多晶SiGe栅极可以减小寄生栅极阻抗。 此外,可以通过在器件栅极附近使用SiGe层来减小沟道电阻,并且可以在沟槽栅极下形成厚的氧化物区域以减小栅极 - 漏极电容。
    • 65. 发明授权
    • Method and mechanism for RTL power optimization
    • RTL功率优化的方法与机制
    • US07007247B1
    • 2006-02-28
    • US10155323
    • 2002-05-24
    • Qi WangSumit Roy
    • Qi WangSumit Roy
    • G06F17/50
    • G06F17/5045G06F2217/78
    • The present invention provides a method and mechanism for optimizing the power consumption of a micro-electronic circuit. According to an embodiment, when optimizing the power consumption of a micro-electronic circuit, one or more candidates for applying one or more optimization techniques may be identified. Then, the one or more candidates may be marked with the one or more optimization techniques within the micro-electronic circuit without altering the data and/or control paths of the circuit. Then, after timing and logic optimization, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique saves power and/or satisfies the timing requirement of the circuit. Further, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique is reducible, and if so, then the technique may be reduced to determine whether such reduction improves the circuit's timing.
    • 本发明提供一种用于优化微电子电路的功耗的方法和机构。 根据实施例,当优化微电子电路的功耗时,可以识别用于应用一个或多个优化技术的一个或多个候选。 然后,可以在微电子电路内标记一个或多个优化技术,而不改变电路的数据和/或控制路径。 然后,在定时和逻辑优化之后,可以评估应用于一个或多个候选的每个省电技术以确定该技术是否节省功率和/或满足电路的定时要求。 此外,可以评估应用于一个或多个候选的每个省电技术以确定该技术是否可减少,如果是,则可以减小该技术以确定这种减小是否改善了电路的定时。