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61. 发明申请

US20050233478A1 STRUCTURE AND METHOD FOR PROVIDING PRECISION PASSIVE ELEMENTS 失效
标题翻译：提供精密无源元件的结构和方法
公开(公告)号：US20050233478A1
公开(公告)日：2005-10-20
申请号：US10709109
申请日：2004-04-14
申请人： Douglas Coolbaugh , Hayden Cranford , Terence Hook , Anthony Stamper
发明人： Douglas Coolbaugh , Hayden Cranford , Terence Hook , Anthony Stamper
IPC分类号： H01L21/00 , H01L23/525 , H01L27/08 , H01P3/08
CPC分类号： H01L27/0802 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.
摘要翻译：在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个具有高于目标值的值，并且具有低于目标值的值。每个无源电路元件还具有与其串联的保险丝。还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择元素。

62. 发明申请

US20050101114A1 Triple damascene fuse 失效
标题翻译：三重镶嵌保险丝
公开(公告)号：US20050101114A1
公开(公告)日：2005-05-12
申请号：US10675177
申请日：2003-09-30
申请人： Timothy Daubenspeck , Thomas McDevitt , William Motsiff , Anthony Stamper
发明人： Timothy Daubenspeck , Thomas McDevitt , William Motsiff , Anthony Stamper
IPC分类号： H01L23/525 , H01L23/532 , H01L21/44 , H01L21/82 , H01L27/10 , H01L29/00
CPC分类号： H01L23/53295 , H01L23/5256 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a conductive fuse for a semiconductor device, comprising: a pair of contact portions integrally connected to a fusible portion by connecting portions; the contact portions thicker than the connecting portions and the connecting portions thicker than the fusible portion; a first dielectric under the connecting portions and the fusible portion and extending between the pair of contact portions; and a second dielectric between the first dielectric and the fusible portion, the second dielectric extending between the connecting portions and defining the length of the fusible portion.
摘要翻译：公开了一种用于半导体器件的导电熔断器，包括：通过连接部分一体地连接到可熔部分的一对接触部分; 所述接触部分比所述连接部分厚，并且所述连接部分比所述可熔部分更厚; 在所述连接部分和所述可熔部分之下的第一电介质，并且在所述一对接触部分之间延伸; 以及在所述第一电介质和所述可熔部分之间的第二电介质，所述第二电介质在所述连接部分之间延伸并且限定所述可熔部分的长度。

63. 发明申请

US20050030149A1 ELECTRICALLY TUNABLE ON-CHIP RESISTOR 失效
标题翻译：电气可控片上电阻
公开(公告)号：US20050030149A1
公开(公告)日：2005-02-10
申请号：US10604609
申请日：2003-08-04
申请人： James Adkisson , Anthony Stamper
发明人： James Adkisson , Anthony Stamper
IPC分类号： H01C10/00 , H01L27/08 , H01C7/10
CPC分类号： H01C10/00 , H01L27/0802
摘要： The present invention discloses a device having a resistor; a heater disposed proximate to the resistor and capable of raising the temperature of the resistor; a dielectric disposed between the heater and the resistor; and a tuner electrically coupled to the resistor, wherein the heater adjusts the resistance of the resistor in response to the tuner.
摘要翻译：本发明公开了一种具有电阻器的器件; 靠近电阻器设置并能够提高电阻器的温度的加热器; 设置在加热器和电阻器之间的电介质; 以及电耦合到所述电阻器的调谐器，其中所述加热器响应于所述调谐器调节所述电阻器的电阻。

64. 发明申请

US20170350666A1 MAGAZINE DEVICE FOR A FIREARM 审中-公开
公开(公告)号：US20170350666A1
公开(公告)日：2017-12-07
申请号：US15174185
申请日：2016-06-06
申请人： Anthony Stamper
发明人： Anthony Stamper
IPC分类号： F41A9/65
CPC分类号： F41A9/65
摘要： A magazine device for a firearm is disclosed herein. The magazine device comprises a generally curved elongate casing, a spring-loaded follower frame, a lighting element, and a multiple transparent windows. The follower frame is configured to traverse from a lower end of the casing to an upper end of the casing in predetermined positions according to the depletion of ammunition positioned on each follower frame. The lighting element is housed proximal to a rear section of the follower frame, where the lighting element is configured to illuminate the vicinity of the follower frame. The transparent windows are positioned on the casing, in alignment with the predetermined positions of the follower frame, where the transparent windows are configured to display the level and number of ammunition left in the follower frame after a firing process.

65. 发明申请

US20080018378A1 STRUCTURE AND METHOD FOR PROVIDING PRECISION PASSIVE ELEMENTS 失效
标题翻译：提供精密无源元件的结构和方法
公开(公告)号：US20080018378A1
公开(公告)日：2008-01-24
申请号：US11865432
申请日：2007-10-01
申请人： Douglas Coolbaugh , Hayden Cranford , Terence Hook , Anthony Stamper
发明人： Douglas Coolbaugh , Hayden Cranford , Terence Hook , Anthony Stamper
IPC分类号： H03H7/00
CPC分类号： H01L27/0802 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.
摘要翻译：在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个具有高于目标值的值，并且具有低于目标值的值。每个无源电路元件还具有与其串联的保险丝。还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择元素。

66. 发明申请

US20070032030A1 METHOD FOR HIGH PERFORMANCE INDUCTOR FABRICATION USING A TRIPLE DAMASCENE PROCESS WITH COPPER BEOL 有权
标题翻译：高性能电感器制造方法使用三倍体大黄方法
公开(公告)号：US20070032030A1
公开(公告)日：2007-02-08
申请号：US11161415
申请日：2005-08-02
申请人： Douglas Coolbaugh , Mete Erturk , Zhong-Xiang He , Anthony Stamper
发明人： Douglas Coolbaugh , Mete Erturk , Zhong-Xiang He , Anthony Stamper
IPC分类号： H01L21/44
CPC分类号： H01L23/5227 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a high performance inductor comprises providing a substrate; forming a plurality of wiring levels over the substrate, wherein each of the wiring levels comprise a dielectric layer; forming a first trench having a first depth in a first dielectric layer on a first wiring level; forming a second trench in the first dielectric layer having a second depth extending at least into a second wiring level; forming a conductor layer substantially simultaneously in the first and second trenches; and removing portions of the conductor layer overfilling the first and second trenches to form a spiral-shaped inductor in the second trench. The method may further comprise forming an interconnect structure in the first trench.
摘要翻译：形成高性能电感器的方法包括：提供衬底; 在衬底上形成多个布线层，其中每个布线层包括介电层; 在第一布线层上形成在第一介电层中具有第一深度的第一沟槽; 在所述第一介电层中形成具有至少延伸至第二布线层的第二深度的第二沟槽; 在第一和第二沟槽中基本上同时地形成导体层; 以及去除超过第一和第二沟槽的导体层的部分，以在第二沟槽中形成螺旋形电感器。该方法还可以包括在第一沟槽中形成互连结构。

67. 发明申请

US20060093924A1 Method and apparatus for correction of defects in lithography masks 失效
标题翻译：用于校正光刻掩模中的缺陷的方法和装置
公开(公告)号：US20060093924A1
公开(公告)日：2006-05-04
申请号：US10904308
申请日：2004-11-03
申请人： James Adkisson , Eric Coker , Christopher Magg , Jed Rankin , Anthony Stamper
发明人： James Adkisson , Eric Coker , Christopher Magg , Jed Rankin , Anthony Stamper
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/72 , G03F1/70
摘要： A method for correction of defects in lithography masks includes determining the existence of mask defects on an original mask, and identifying a stitchable zone around each of the mask defects found on the original mask. Each of the identified stitchable zones on the original mask is blocked out such that circuitry within the stitchable zones is not printed out during exposure of the original mask. A repair mask is formed, the repair mask including corrected circuit patterns from each of the identified stitchable zones.
摘要翻译：用于校正光刻掩模中的缺陷的方法包括确定原始掩模上的掩模缺陷的存在，以及识别在原始掩模上发现的每个掩模缺陷周围的可缝合区域。原始掩模上的每个识别的可缝合区域被阻挡，使得在原始掩模曝光期间不能打印出可缝合区域内的电路。形成修复掩模，修复掩模包括来自每个识别的可缝合区域的校正电路图案。

68. 发明申请

US20060012052A1 DUAL DAMASCENE WIRING AND METHOD 有权
标题翻译：双面接线和方法
公开(公告)号：US20060012052A1
公开(公告)日：2006-01-19
申请号：US10710478
申请日：2004-07-14
申请人： Thomas McDevitt , Anthony Stamper
发明人： Thomas McDevitt , Anthony Stamper
IPC分类号： H01L23/48
CPC分类号： H01L21/76838 , H01L21/76802 , H01L21/76808 , H01L23/5223 , H01L23/5227 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating a dual damascene interconnect structure, the structure including a dual damascene wire in a dielectric layer, the dual damascene wires extending a distance into the dielectric layer less than the thickness of the dielectric layer and dual damascene via bars integral with and extending from bottom surfaces of the dual damascene wires to a bottom surface of the dielectric layer.
摘要翻译：一种制造双镶嵌互连结构的结构和方法，该结构包括在介电层中的双镶嵌线，双镶嵌线延伸到电介质层中的距离小于电介质层的厚度和通过与并且从双镶嵌线的底表面延伸到介电层的底表面。

69. 发明申请

US20050227449A1 METHOD FOR MANUFACTURING SELF-COMPENSATING RESISTORS WITHIN AN INTEGRATED CIRCUIT 有权
标题翻译：在集成电路中制造自补偿电阻的方法
公开(公告)号：US20050227449A1
公开(公告)日：2005-10-13
申请号：US10709039
申请日：2004-04-08
申请人： William Murphy , Edmund Sprogis , Anthony Stamper , Erick Walton
发明人： William Murphy , Edmund Sprogis , Anthony Stamper , Erick Walton
IPC分类号： H01L21/02 , H01L27/08 , H01L29/76
CPC分类号： H01L28/20 , H01L27/0802 , Y10T29/49082 , Y10T29/49085
摘要： A method for manufacturing a self-compensating resistor within an integrated circuit is disclosed. The self-compensating resistor includes a first resistor and a second resistor. The first resistor having a first resistance value is initially formed, and then the second resistor having a second resistance value is subsequently formed. The second resistor is connected in series with the first resistor. The second resistance value is less than the first resistance value, but the total resistance value of the first and second resistors lies beyond a desired target resistance range. Finally, an electric current is sent to the second resistor to change the dimension of the second resistor such that the total resistance value of the first and second resistors falls within the desired target resistance range.
摘要翻译：公开了一种在集成电路内制造自补偿电阻器的方法。自补偿电阻器包括第一电阻器和第二电阻器。初始形成具有第一电阻值的第一电阻器，然后形成具有第二电阻值的第二电阻器。第二个电阻与第一个电阻串联。第二电阻值小于第一电阻值，但是第一和第二电阻器的总电阻值超过期望的目标电阻范围。最后，向第二电阻器发送电流以改变第二电阻器的尺寸，使得第一和第二电阻器的总电阻值落在期望的目标电阻范围内。

70. 发明申请

US20080102543A1 INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY OXIDATION 有权
标题翻译：通过氧化增加电阻的电阻
公开(公告)号：US20080102543A1
公开(公告)日：2008-05-01
申请号：US11968686
申请日：2008-01-03
申请人： Arne Ballantine , Daniel Edelstein , Anthony Stamper
发明人： Arne Ballantine , Daniel Edelstein , Anthony Stamper
IPC分类号： H01L21/66 , H01L21/31
CPC分类号： C23C8/02 , C23C8/04 , C23C8/10 , C23C8/24 , C25D11/00 , C25D11/02 , C25D11/026 , H01C7/006 , H01C17/26 , H01L21/263 , H01L27/0802 , H01L29/8605 , Y10S257/904 , Y10S257/914
摘要： A method for increasing an electrical resistance of a resistor that is within a semiconductor structure. A fraction of a surface layer of the resistor is oxidized with oxygen particles. In an embodiment, the fraction of the surface layer is heated by a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen particles as gaseous oxygen-comprising molecules. In an embodiment, the semiconductor structure is immersed in a chemical solution which includes the oxygen particles, wherein the oxygen particles includes oxygen-comprising liquid molecules, oxygen ions, or an oxygen-comprising gas dissolved in the chemical solution under pressurization. In an embodiment, the resistor is tested to determine whether the electrical resistance of the resistor after being oxidized with the oxygen particles is within a tolerance of a predetermined target resistance.
摘要翻译：一种用于增加在半导体结构内的电阻器的电阻的方法。电阻的表面层的一部分被氧颗粒氧化。在一个实施方案中，表面层的分数由颗粒束加热，使得半导体结构在包含作为气态含氧分子的氧颗粒的室内。在一个实施方案中，将半导体结构浸入包括氧颗粒的化学溶液中，其中氧颗粒包括在加压下溶解在化学溶液中的含氧液体分子，氧离子或含氧气体。在一个实施例中，测试电阻器以确定在用氧颗粒氧化后电阻器的电阻是否在预定目标电阻的容限内。

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