专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07257024B2 Minimizing adjacent wordline disturb in a memory device 有权
公开(公告)号：US07257024B2
公开(公告)日：2007-08-14
申请号：US11417575
申请日：2006-05-04
申请人： Paul J. Rudeck , Andrei Mihnea , Andrew Bicksler
发明人： Paul J. Rudeck , Andrei Mihnea , Andrew Bicksler
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

62. 发明授权

US07215571B2 Method for reducing drain disturb in programming 有权
标题翻译：减少编程中漏水干扰的方法
公开(公告)号：US07215571B2
公开(公告)日：2007-05-08
申请号：US10931689
申请日：2004-09-01
申请人： Andrei Mihnea , Vinod Lakhani
发明人： Andrei Mihnea , Vinod Lakhani
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3427 , G11C16/3418
摘要： For a multi-sectored flash memory array with bitlines spanning multiple erase blocks, a bias scheme for programming an address in any erase sector while minimizing drain voltage induced disturb to cells in unselected erase sectors sharing the same bitlines.
摘要翻译：对于具有横跨多个擦除块的位线的多扇区闪速存储器阵列，用于对任何擦除扇区中的地址进行编程的偏置方案，同时最小化漏极电压对共享相同位线的未选择擦除扇区中的单元的干扰。

63. 发明申请

US20060198221A1 Minimizing adjacent wordline disturb in a memory device 有权
公开(公告)号：US20060198221A1
公开(公告)日：2006-09-07
申请号：US11417574
申请日：2006-05-04
申请人： Paul Rudeck , Andrei Mihnea , Andrew Bicksler
发明人： Paul Rudeck , Andrei Mihnea , Andrew Bicksler
IPC分类号： G11C7/02
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

64. 发明授权

US07088619B2 Method for programming and erasing an NROM cell 有权
公开(公告)号：US07088619B2
公开(公告)日：2006-08-08
申请号：US11047809
申请日：2005-02-01
申请人： Andrei Mihnea
发明人： Andrei Mihnea
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/0466 , G11C16/10
摘要： A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled to the gate input. A constant positive current is input to one of the source/drain regions. The remaining source/drain region is either allowed to float, is coupled to a ground potential, or is coupled to the first source/drain region.

65. 发明申请

US20060133152A1 Method for programming and erasing an NROM cell 有权
公开(公告)号：US20060133152A1
公开(公告)日：2006-06-22
申请号：US11339399
申请日：2006-01-25
申请人： Andrei Mihnea
发明人： Andrei Mihnea
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/0466 , G11C16/10
摘要： A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled to the gate input. A constant positive current is input to one of the source/drain regions. The remaining source/drain region is either allowed to float, is coupled to a ground potential, or is coupled to the first source/drain region.

66. 发明授权

US06873550B2 Method for programming and erasing an NROM cell 有权
标题翻译：用于编程和擦除NROM单元的方法
公开(公告)号：US06873550B2
公开(公告)日：2005-03-29
申请号：US10636173
申请日：2003-08-07
申请人： Andrei Mihnea
发明人： Andrei Mihnea
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C16/0475 , G11C16/0466 , G11C16/10
摘要： A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled to the gale input. A constant positive current is input to one of the source/drain regions. The remaining source/drain region is either allowed to float, is coupled to a ground potential, or is coupled to the first source/drain region.
摘要翻译：氮化物只读存储器（NROM）单元可以通过向栅极输入施加斜坡电压，对两个源极/漏极区中的一个施加恒定电压，并将剩余的源极/漏极区的接地电位编程。为了擦除NROM单元，将恒定电压耦合到大风输入端。恒定的正电流被输入到源/漏区之一。剩余的源极/漏极区域被允许浮动，耦合到接地电位，或耦合到第一源极/漏极区域。

67. 发明授权

US08557654B2 Punch-through diode 有权
标题翻译：穿通二极管
公开(公告)号：US08557654B2
公开(公告)日：2013-10-15
申请号：US12966735
申请日：2010-12-13
申请人： Peter Rabkin , Andrei Mihnea
发明人： Peter Rabkin , Andrei Mihnea
IPC分类号： H01L21/329 , H01L21/33 , H01L27/02 , H01L23/60 , H01L23/62
CPC分类号： H01L27/0255 , G11C2213/72 , G11C2213/74 , H01L27/2409 , H01L27/2481 , H01L29/6609 , H01L29/66121 , H01L29/861 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A punch-through diode and method of fabricating the same are disclosed herein. The punch-through diode may be used as a steering element in a memory device having a reversible resistivity-switching element. For example, a memory cell may include a reversible resistivity-switching element in series with a punch-through diode. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. In other words, the ratio of Ion/Ioff is high. Therefore, the punch-through diode is compatible with bipolar switching in cross-point memory arrays having resistive switching elements.
摘要翻译：本文公开了穿通二极管及其制造方法。穿通二极管可以用作具有可逆电阻率开关元件的存储器件中的转向元件。例如，存储单元可以包括与穿通二极管串联的可逆电阻率开关元件。穿通二极管允许交叉点存储器阵列的双极性操作。穿通二极管可具有对称的非线性电流/电压关系。穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。换句话说，Ion / Ioff的比例很高。因此，穿通二极管与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。

68. 发明授权

US08351243B2 Transistor driven 3D memory 有权
标题翻译：晶体管驱动的3D存储器
公开(公告)号：US08351243B2
公开(公告)日：2013-01-08
申请号：US12947553
申请日：2010-11-16
申请人： Andrei Mihnea , George Samachisa
发明人： Andrei Mihnea , George Samachisa
IPC分类号： G11C11/00 , H01L29/06
CPC分类号： G11C13/003 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/79 , H01L27/2454 , H01L27/2463
摘要： A nonvolatile memory device with a first conductor extending in a first direction and a semiconductor element above the first conductor. The semiconductor element includes a source, a drain and a channel of a field effect transistor (JFET or MOSFET). The nonvolatile memory device also includes a second conductor above the semiconductor element, the second conductor extending in a second direction. The nonvolatile memory device also includes a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element. The JFET or MOSFET includes a gate adjacent to the channel, and the MOSFET gate being self-aligned with the first conductor.
摘要翻译：一种非易失性存储器件，具有沿第一方向延伸的第一导体和位于第一导体上方的半导体元件。半导体元件包括场效应晶体管（JFET或MOSFET）的源极，漏极和沟道。非易失性存储器件还包括在半导体元件上方的第二导体，第二导体沿第二方向延伸。非易失性存储器件还包括设置在第一导体和半导体元件之间或第二导体与半导体元件之间的电阻率切换材料。 JFET或MOSFET包括与沟道相邻的栅极，并且MOSFET栅极与第一导体自对准。

69. 发明申请

US20120302029A1 PUNCH-THROUGH DIODE STEERING ELEMENT 有权
标题翻译： PUNCH-THROUGH二极管转向元件
公开(公告)号：US20120302029A1
公开(公告)日：2012-11-29
申请号：US13571100
申请日：2012-08-09
申请人： Andrei Mihnea , Deepak C. Sekar , George Samachisa , Roy Scheuerlein , Li Xiao
发明人： Andrei Mihnea , Deepak C. Sekar , George Samachisa , Roy Scheuerlein , Li Xiao
IPC分类号： H01L21/02
CPC分类号： G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/32 , G11C2213/34 , G11C2213/72 , H01L27/24
摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.
摘要翻译：描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。穿通二极管允许交叉点存储器阵列的双极性操作。穿通二极管可具有对称的非线性电流/电压关系。穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

70. 发明申请

US20120120709A1 Transistor Driven 3D Memory 有权
标题翻译：晶体管驱动的3D存储器
公开(公告)号：US20120120709A1
公开(公告)日：2012-05-17
申请号：US12947553
申请日：2010-11-16
申请人： Andrei Mihnea , George Samachisa
发明人： Andrei Mihnea , George Samachisa
IPC分类号： G11C11/56 , H01L21/8239 , H01L45/00
CPC分类号： G11C13/003 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/79 , H01L27/2454 , H01L27/2463
摘要： A nonvolatile memory device with a first conductor extending in a first direction and a semiconductor element above the first conductor. The semiconductor element includes a source, a drain and a channel of a field effect transistor (JFET or MOSFET). The nonvolatile memory device also includes a second conductor above the semiconductor element, the second conductor extending in a second direction. The nonvolatile memory device also includes a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element. The JFET or MOSFET includes a gate adjacent to the channel, and the MOSFET gate being self-aligned with the first conductor.
摘要翻译：一种非易失性存储器件，具有沿第一方向延伸的第一导体和位于第一导体上方的半导体元件。半导体元件包括场效应晶体管（JFET或MOSFET）的源极，漏极和沟道。非易失性存储器件还包括在半导体元件上方的第二导体，第二导体沿第二方向延伸。非易失性存储器件还包括设置在第一导体和半导体元件之间或第二导体与半导体元件之间的电阻率切换材料。 JFET或MOSFET包括与沟道相邻的栅极，并且MOSFET栅极与第一导体自对准。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式