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61. 发明申请

US20090249349A1 Power-Efficient Thread Priority Enablement 有权
标题翻译：高效的线程优先级启用
公开(公告)号：US20090249349A1
公开(公告)日：2009-10-01
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
IPC分类号： G06F9/46
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译：一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。说明性实施例确定了处理器的目标功率效率模式。一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。

62. 发明申请

US20090199020A1 METHOD AND SYSTEM OF MULTI-CORE MICROPROCESSOR POWER MANAGEMENT AND CONTROL VIA PER-CHIPLET, PROGRAMMABLE POWER MODES 有权
标题翻译：多芯片微处理器电源管理和控制方法与系统，可编程电源模式
公开(公告)号：US20090199020A1
公开(公告)日：2009-08-06
申请号：US12023536
申请日：2008-01-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171
摘要： A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor. The global power management controller issues commands either directly for a specific chiplet out of the plurality of chiplets or to the plurality of chiplets and the control slave bus translates the command into sub-commands dedicated to specific chiplets within the plurality of chiplets. Each chiplet may be set to separate power levels.
摘要翻译：提供了一种计算机实现的方法和用于管理多核微处理器中的电力的系统。小电流中的电源管理控制微体系结构转换包括功率设置的第一命令。小巧包括处理器核心和相关联的存储器高速缓存。功率管理控制微体系结构包括功率模式寄存器，功率模式调节器，转换器和微架构电源管理技术。电源管理控制微架构根据功率设置设置微体系结构电源管理技术。全球电源管理控制器发出第一个命令。全局功率管理控制器可以驻留在微处理器上或者关闭。全局功率管理控制器直接针对多个小芯片中的特定小时或多个小芯片发出命令，并且控制从总线将命令转换为专用于多个小芯片内的特定小芯片的子命令。每个小穗可以设置为分开的功率水平。

63. 发明申请

US20060101238A1 Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches 有权
标题翻译：多线程处理器中的自适应提取门控，提取控制和控制提取的方法
公开(公告)号：US20060101238A1
公开(公告)日：2006-05-11
申请号：US11228781
申请日：2005-09-16
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard Eickemeyer , Lee Eisen , Philip Emma , John Griswell , Zhigang Hu , Hung Le , Douglas Logan , Balaram Sinharoy
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard Eickemeyer , Lee Eisen , Philip Emma , John Griswell , Zhigang Hu , Hung Le , Douglas Logan , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3867
摘要： A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.
摘要翻译：多线程处理器，用于多线程处理器的获取控制以及在多线程处理器中获取的方法。监视处理器事件和使用（EU）符号，用于指示管道执行线程状态的下游管道条件。对于不能接收获取的高速缓存内容的任何线程，例如由于线程已满或停顿，跳过指令高速缓存提取。此外，可以针对相同的线程选择连续的提取，例如在分支误预测中。因此，处理器避免浪费电力不必要的或放置保持器提取。

64. 发明授权

US09182991B2 Multi-threaded processor instruction balancing through instruction uncertainty 有权
标题翻译：多线程处理器指令平衡通过指令不确定
公开(公告)号：US09182991B2
公开(公告)日：2015-11-10
申请号：US13366999
申请日：2012-02-06
申请人： Alper Buyuktosunoglu , Brian R. Prasky , Vijayalakshmi Srinivasan
发明人： Alper Buyuktosunoglu , Brian R. Prasky , Vijayalakshmi Srinivasan
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3851
摘要： A computer system for instruction execution includes a processor having a pipeline. The system is configured to perform a method including fetching, in the pipeline, a plurality of instructions, wherein the plurality of instructions includes a plurality of branch instructions, for each of the plurality of branch instructions, assigning a branch uncertainty to each of the plurality of branch instructions, for each of the plurality of instructions, assigning an instruction uncertainty that is a summation of branch uncertainties of older unresolved branches and balancing the instructions, based on a current summation of instruction uncertainty, in the pipeline.
摘要翻译：用于指令执行的计算机系统包括具有流水线的处理器。该系统被配置为执行一种方法，包括在流水线中取出多个指令，其中多个指令包括多个分支指令，对于多个分支指令中的每一个，向多个指令中的每一个指派分支不确定度对于所述多个指令中的每一个指令，分配指示不确定性，所述指令不确定性是基于所述流水线中的指令不确定性的当前求和而作为旧的未解析分支的分支不确定性的总和并且平衡所述指令。

65. 发明授权

US08799710B2 3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits 有权
公开(公告)号：US08799710B2
公开(公告)日：2014-08-05
申请号：US13535676
申请日：2012-06-28
申请人： Alper Buyuktosunoglu , Philip G. Emma , Allan M. Hartstein , Michael B. Healy , Krishnan K. Kailas
发明人： Alper Buyuktosunoglu , Philip G. Emma , Allan M. Hartstein , Michael B. Healy , Krishnan K. Kailas
IPC分类号： G06F11/00
CPC分类号： G06F15/7832 , G06F1/324 , G06F1/3287 , G06F1/329 , Y02D10/126 , Y02D10/171 , Y02D10/24
摘要： A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.

66. 发明申请

US20140006750A1 3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS TO ENABLE RELIABLE OPERATION OF PROCESSORS AT SPEEDS ABOVE SPECIFIED LIMITS 有权
标题翻译： 3-D堆叠式多处理器结构和方法，使加工程序的可靠运行速度超过指定的限制
公开(公告)号：US20140006750A1
公开(公告)日：2014-01-02
申请号：US13602777
申请日：2012-09-04
申请人： Alper Buyuktosunoglu , Philip G. Emma , Allan M. Hartstein , Michael B. Healy , Krishnan K. Kailas
发明人： Alper Buyuktosunoglu , Philip G. Emma , Allan M. Hartstein , Michael B. Healy , Krishnan K. Kailas
IPC分类号： G06F15/76
CPC分类号： G06F15/7832 , G06F1/324 , G06F1/3287 , G06F1/329 , Y02D10/126 , Y02D10/171 , Y02D10/24
摘要： A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.
摘要翻译：三维（3-D）处理器系统包括堆叠配置的第一处理器芯片和第二处理器芯片。第一处理器芯片包括具有第一组状态寄存器的第一处理器。第二处理器芯片包括具有对应于第一组状态寄存器的第二组状态寄存器的第二处理器。第一和第二处理器通过第一和第二处理器芯片之间的垂直连接连接。模式控制电路以多种操作模式之一操作处理器系统。在一种操作模式中，第一处理器是有效的，而第二处理器是不活动的，并且第一处理器以大于第一处理器的最大安全速度的速度操作，并且第一处理器使用第二处理器的第二组状态寄存器第二处理器来检查第一处理器的状态。

67. 发明申请

US20130283006A1 3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS FOR MULTIMODAL OPERATION OF SAME 审中-公开
标题翻译： 3-D堆叠多处理器结构及其多种操作方法
公开(公告)号：US20130283006A1
公开(公告)日：2013-10-24
申请号：US13602807
申请日：2012-09-04
申请人： Alper Buyuktosunoglu , Philip G. Emma , Allan M. Hartstein , Michael B. Healy , Krishnan Kunjunny Kailas
发明人： Alper Buyuktosunoglu , Philip G. Emma , Allan M. Hartstein , Michael B. Healy , Krishnan Kunjunny Kailas
IPC分类号： G06F15/80
CPC分类号： G06F15/7867 , H01L25/0657 , H01L2924/0002 , Y02D10/12 , Y02D10/13 , H01L2924/00
摘要： Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.
摘要翻译：提供三维（3-D）处理器结构，其通过以堆叠配置连接处理器构成。例如，处理器系统包括包括第一处理器的第一处理器芯片和包括第二处理器的第二处理器芯片。第一和第二处理器芯片以堆叠配置连接，第一和第二处理器通过第一和第二处理器芯片之间的垂直连接而连接。处理器系统还包括模式控制电路，用于选择性地将第一和第二处理器芯片的第一和第二处理器配置为以多种操作模式中的一种操作，其中处理器可以被选择性地配置为独立地操作以聚合资源，共享资源和/或组合以形成单个处理器映像。

68. 发明申请

US20130205118A1 MULTI-THREADED PROCESSOR INSTRUCTION BALANCING THROUGH INSTRUCTION UNCERTAINTY 有权
标题翻译：多线程处理器通过指令不确定的平衡
公开(公告)号：US20130205118A1
公开(公告)日：2013-08-08
申请号：US13366999
申请日：2012-02-06
申请人： Alper Buyuktosunoglu , Brian R. Prasky , Vijayalakshmi Srinivasan
发明人： Alper Buyuktosunoglu , Brian R. Prasky , Vijayalakshmi Srinivasan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/3851
摘要： A computer system for instruction execution includes a processor having a pipeline. The system is configured to perform a method including fetching, in the pipeline, a plurality of instructions, wherein the plurality of instructions includes a plurality of branch instructions, for each of the plurality of branch instructions, assigning a branch uncertainty to each of the plurality of branch instructions, for each of the plurality of instructions, assigning an instruction uncertainty that is a summation of branch uncertainties of older unresolved branches and balancing the instructions, based on a current summation of instruction uncertainty, in the pipeline.
摘要翻译：用于指令执行的计算机系统包括具有流水线的处理器。该系统被配置为执行一种方法，包括在流水线中取出多个指令，其中多个指令包括多个分支指令，对于多个分支指令中的每一个，向多个指令中的每一个指派分支不确定度对于所述多个指令中的每一个指令，分配指示不确定性，所述指令不确定性是基于所述流水线中的指令不确定性的当前求和而作为旧的未解析分支的分支不确定性的总和并且平衡所述指令。

69. 发明授权

US07698249B2 System and method for predicting hardware and/or software metrics in a computer system using models 有权
标题翻译：用于使用模型预测计算机系统中的硬件和/或软件度量的系统和方法
公开(公告)号：US07698249B2
公开(公告)日：2010-04-13
申请号：US11625392
申请日：2007-01-22
申请人： Alper Buyuktosunoglu , Ruhi Sarikaya
发明人： Alper Buyuktosunoglu , Ruhi Sarikaya
IPC分类号： G06F17/00 , G06F19/00
CPC分类号： G05B13/048
摘要： An objective function is dynamically chosen from a pool of available objective functions, and a prediction model is dynamically chosen from a pool of available prediction models. Points of inflection are determined for the chosen objective function, based on past values of a metric, to obtain a set of equations that can be solved to obtain model parameters associated with the chosen prediction model. The equations are solved to obtain the model parameters, and a future value of the metric is predicted based on (i) at least some of the past values of the metric and (ii) the chosen prediction model, with the obtained associated model parameters.
摘要翻译：从可用的目标函数池动态地选择目标函数，并且从可用的预测模型池中动态地选择预测模型。基于度量的过去值来确定所选择的目标函数的拐点，以获得可以被求解以获得与所选预测模型相关联的模型参数的一组方程式。求解等式以获得模型参数，并且基于（i）度量的至少一些过去值和（ii）所选择的预测模型以及获得的相关联的模型参数来预测度量的未来值。

70. 发明申请

US20100057404A1 Optimal Performance and Power Management With Two Dependent Actuators 审中-公开
标题翻译：具有两个独立执行器的最佳性能和电源管理
公开(公告)号：US20100057404A1
公开(公告)日：2010-03-04
申请号：US12201877
申请日：2008-08-29
申请人： Gero Dittmann , Alper Buyuktosunoglu , Indira Nair , Reinaldo A. Bergamaschi
发明人： Gero Dittmann , Alper Buyuktosunoglu , Indira Nair , Reinaldo A. Bergamaschi
IPC分类号： G06F19/00 , G05B13/02
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Techniques for processor chip power management and performance optimization are provided. In one aspect, a method for maximizing performance of a processor chip within a given power consumption budget is provided. The method comprises the following steps. A power consumption and performance of the processor chip at all possible voltage level and frequency combinations is predicted. The processor chip is adjusted to the voltage level and frequency combination that provides the highest performance while having a power consumption that does not exceed the power budget. After a time interval t1, the frequency of the processor chip is varied to accommodate for any shift in workload to maintain the highest performance within the power budget. After a time interval t2, the adjust and vary steps are repeated, wherein time interval t2 is greater than time interval t1.
摘要翻译：提供了处理器芯片功率管理和性能优化的技术。在一个方面，提供了一种用于在给定功耗预算内最大化处理器芯片的性能的方法。该方法包括以下步骤。预测在所有可能的电压电平和频率组合下的处理器芯片的功耗和性能。处理器芯片被调整到提供最高性能的电压电平和频率组合，同时具有不超过功率预算的功耗。在时间间隔t1之后，改变处理器芯片的频率以适应任何工作量的变化，以在功率预算内维持最高性能。在时间间隔t2之后，重复调整和改变步骤，其中时间间隔t2大于时间间隔t1。

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