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61. 发明申请

US20150006717A1 TRACKING MODE OF A PROCESSING DEVICE IN INSTRUCTION TRACING SYSTEMS 审中-公开
标题翻译：指令跟踪系统中处理设备的跟踪模式
公开(公告)号：US20150006717A1
公开(公告)日：2015-01-01
申请号：US14126313
申请日：2013-06-27
申请人： Thilo Schmitt , Peter Lachner , Beeman Strong , Ofer Levy , Thomas Toll , Matthew Merten , Tong Li , Ravi Rajwar , Konrad Lai
发明人： Thilo Schmitt , Peter Lachner , Beeman Strong , Ofer Levy , Thomas Toll , Matthew Merten , Tong Li , Ravi Rajwar , Konrad Lai
IPC分类号： H04L12/26
CPC分类号： G06F9/30189 , G06F11/3636
摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.
摘要翻译：根据本文公开的实施例，提供了用于跟踪指令跟踪系统中的处理设备的模式的系统和方法。该方法可以包括接收处理设备的当前执行模式中的改变的指示。该方法还可以包括确定接收到的指示的当前执行模式不同于IT模块先前生成的第一执行模式（EM）分组的执行模式的值。该方法还可以包括基于确定当前执行模式不同而生成第二EM分组，其提供处理设备的当前执行模式的值以指示用于跟踪中的指令的执行模式的改变由IT模块生成。该方法还可以包括在分组日志中生成具有n位模式模式的事务存储器（TMX）分组。 n至少为2，n位模式表示TMX操作的事务状态。

62. 发明申请

US20140006698A1 Hybrid Cache State And Filter Tracking Of Memory Operations During A Transaction 有权
标题翻译：混合缓存状态和过滤器跟踪事务期间的内存操作
公开(公告)号：US20140006698A1
公开(公告)日：2014-01-02
申请号：US13535788
申请日：2012-06-28
申请人： Robert S. Chappell , Ravi Rajwar , Zhongying Zhang , Jason A. Bessette
发明人： Robert S. Chappell , Ravi Rajwar , Zhongying Zhang , Jason A. Bessette
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0842 , G06F9/467 , G06F12/0897
摘要： In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，高速缓存存储器可以存储多条高速缓存线，每条高速缓存行包括写入字段以存储写入指示符，以指示在事务性存储器的事务期间是否已经推测写入数据，以及读取集字段以存储多个读取设置指示符，每个指示符指示对应的线程在交易已经提交之前是否已经读取数据。与高速缓冲存储器相关联的压缩过滤器包括第一过滤器存储器，用于在事务已经提交之前存储由第一线程线程读取的高速缓存线的高速缓存行地址的表示。描述和要求保护其他实施例。

63. 发明授权

US08180977B2 Transactional memory in out-of-order processors 有权
标题翻译：无序处理器中的事务性内存
公开(公告)号：US08180977B2
公开(公告)日：2012-05-15
申请号：US11394687
申请日：2006-03-30
申请人： Ravi Rajwar , Haitham H. Akkary , Konrad Lai
发明人： Ravi Rajwar , Haitham H. Akkary , Konrad Lai
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863 , G06F12/0802 , G06F13/1626
摘要： Methods and apparatus to provide transactional memory execution in out-of-order processors are described. In one embodiment, a stored value corresponds to the number of transactional memory access requests that are uncommitted. The stored value may be used to provide nested recovery in case of an error, fault, etc. in accordance with a described embodiment.
摘要翻译：描述了在乱序处理器中提供事务性存储器执行的方法和装置。在一个实施例中，存储的值对应于未提交的事务存储器访问请求的数量。根据所描述的实施例，存储的值可以用于在错误，故障等的情况下提供嵌套恢复。

64. 发明授权

US08117392B2 Method and apparatus for efficient ordered stores over an interconnection network 有权
标题翻译：通过互连网络实现有效存储的方法和装置
公开(公告)号：US08117392B2
公开(公告)日：2012-02-14
申请号：US10691176
申请日：2003-10-22
申请人： Mark J. Charney , Ravi Rajwar , Pritpal S. Ahuja , Matthew C. Mattina
发明人： Mark J. Charney , Ravi Rajwar , Pritpal S. Ahuja , Matthew C. Mattina
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： G06F12/0813 , G06Q30/0601
摘要： A physically distributed cache memory system includes an interconnection network, first level cache memory slices, and second level cache memory slices. The first level cache memory slices are coupled to the interconnection network to generate tagged ordered store requests. Each tagged ordered store requests has a tag including requester identification and a store sequence token. The second level cache memory slices are coupled to the interconnection network to execute ordered store requests in-order across the physically distributed cache memory system in response to each tag of the tagged ordered store requests.
摘要翻译：物理分布式高速缓冲存储器系统包括互连网络，第一级高速缓存存储器片和第二级高速缓存存储器片。第一级缓存存储器片耦合到互连网络以生成标记的有序存储请求。每个标记的有序存储请求都具有包括请求者标识和存储序列令牌的标签。第二级高速缓存存储器片耦合到互连网络，以响应于标记的有序存储请求的每个标签跨物理分布式高速缓冲存储器系统按顺序执行有序存储请求。

65. 发明申请

US20110153989A1 SYNCHRONIZING SIMD VECTORS 有权
标题翻译：同步SIMD矢量图
公开(公告)号：US20110153989A1
公开(公告)日：2011-06-23
申请号：US12644529
申请日：2009-12-22
申请人： Ravi Rajwar , Andrew T. Forsyth
发明人： Ravi Rajwar , Andrew T. Forsyth
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30087
摘要： A vector compare-and-exchange operation is performed by: decoding by a decoder in a processing device, a single instruction specifying a vector compare-and-exchange operation for a plurality of data elements between a first storage location, a second storage location, and a third storage location; issuing the single instruction for execution by an execution unit in the processing device; and responsive to the execution of the single instruction, comparing data elements from the first storage location to corresponding data elements in the second storage location; and responsive to determining a match exists, replacing the data elements from the first storage location with corresponding data elements from the third storage location.
摘要翻译：通过以下操作来执行向量比较和交换操作：通过处理设备中的解码器进行解码，指定在第一存储位置，第二存储位置和第二存储位置之间的多个数据元素的向量比较和交换操作的单个指令，和第三存储位置; 发出由处理装置中的执行单元执行的单个指令; 并且响应于所述单个指令的执行，将来自所述第一存储位置的数据元素与所述第二存储位置中的相应数据元素进行比较; 并且响应于确定匹配存在，用来自第三存储位置的相应数据元素从第一存储位置替换数据元素。

66. 发明申请

US20070186215A1 Concurrent Execution of Critical Sections by Eliding Ownership of Locks 有权
标题翻译：通过确定锁定所有权并行执行关键部分
公开(公告)号：US20070186215A1
公开(公告)日：2007-08-09
申请号：US11539731
申请日：2006-10-09
申请人： Ravi Rajwar , James Goodman
发明人： Ravi Rajwar , James Goodman
IPC分类号： G06F9/46
CPC分类号： G06F9/528 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3009 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/52 , G06F12/0808 , G06F12/0844 , G06F12/0891 , G06F12/12 , G06F12/128 , G06F12/1458 , G06F12/1475 , G06F2212/1041 , G06F2212/1052 , G06F2212/283 , G06F2212/62 , G06F2212/69
摘要： One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.
摘要翻译：本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

67. 发明授权

US06460124B1 Method of using delays to speed processing of inferred critical program portions 有权
标题翻译：使用延迟加速推断的关键程序部分的方法
公开(公告)号：US06460124B1
公开(公告)日：2002-10-01
申请号：US09693030
申请日：2000-10-20
申请人： Alain Kagi , James R. Goodman , Ravi Rajwar
发明人： Alain Kagi , James R. Goodman , Ravi Rajwar
IPC分类号： G06F1208
CPC分类号： G06F12/0806 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834 , G06F9/528
摘要： Critical sections of a program, providing exclusive access to shared data in a multi-processor architecture may be inferred from standard instructions and used to invoke a cache protocol that delays the response of requests of other cache and thus counter intuitively improving performance of the system. During this delay, read-only copies of data may be provided and the delay may recognize two priorities of requests, one of which is not delayed so as to improve the release of locks held by different processors.
摘要翻译：可以从标准指令推断程序的关键部分，提供对多处理器架构中的共享数据的独占访问，并且用于调用延迟其他缓存的请求的响应的缓存协议，从而直观地改善系统的性能。在该延迟期间，可以提供数据的只读副本，并且延迟可以识别请求的两个优先级，其中一个优先级不被延迟，以便改善由不同处理器保持的锁的释放。

68. 发明申请

US20160283232A1 Instruction and Logic for Speculative Request Support for Prefetching 审中-公开
标题翻译：提取请求支持预取的指令和逻辑
公开(公告)号：US20160283232A1
公开(公告)日：2016-09-29
申请号：US14671569
申请日：2015-03-27
申请人： Raanan Sade , Ryan L. Carlson , Larisa Novakovsky , Erik G. Hallnor , Ravi Rajwar , Roman Dementiev
发明人： Raanan Sade , Ryan L. Carlson , Larisa Novakovsky , Erik G. Hallnor , Ravi Rajwar , Roman Dementiev
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30047 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/46
摘要： A processor includes a core and a prefetcher. The prefetcher includes logic to issue a request for data including a requested prefetch. The core includes logic to receive an indication of the request, determine whether the request is for a restricted region of memory, and, based upon whether the request is for the restricted region of memory, allow or deny the request.
摘要翻译：处理器包括核心和预取器。预取器包括发出对包括请求的预取的数据的请求的逻辑。核心包括用于接收请求的指示的逻辑，确定请求是否是针对存储器的受限区域，以及基于该请求是针对该存储器的受限区域，允许还是拒绝该请求。

69. 发明申请

US20160246606A1 Method, apparatus, and system for speculative abort control mechanisms 审中-公开
公开(公告)号：US20160246606A1
公开(公告)日：2016-08-25
申请号：US14998249
申请日：2015-12-26
申请人： Martin G. Dixon , Ravi Rajwar , Konrad K. Lai , Robert S. Chappell , Rajesh S. Parthasarathy , Alexandre J. Farcy , Ilhyun Kim , Prakash Math , Matthew Merten , Vijakumar Kadgi
发明人： Martin G. Dixon , Ravi Rajwar , Konrad K. Lai , Robert S. Chappell , Rajesh S. Parthasarathy , Alexandre J. Farcy , Ilhyun Kim , Prakash Math , Matthew Merten , Vijakumar Kadgi
IPC分类号： G06F9/38 , G06F9/30 , G06F12/08 , G06F9/46 , G06F12/10
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/3859 , G06F9/3861 , G06F9/467 , G06F9/528 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0895 , G06F12/0897 , G06F12/1027 , G06F12/1045 , G06F13/1673 , G06F13/4068 , G06F13/4282 , G06F2212/452 , G06F2212/50 , G06F2212/60 , G06F2212/602 , G06F2212/621 , G06F2212/68 , G06F2212/682
摘要： An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

70. 发明申请

US20160210177A1 Method, apparatus, and system for speculative abort control mechanisms 审中-公开
公开(公告)号：US20160210177A1
公开(公告)日：2016-07-21
申请号：US14998207
申请日：2015-12-26
申请人： Martin G. Dixon , Ravi Rajwar , Konrad K. Lai , Robert S. Chappell , Rajesh S. Parthasarathy , Alexandre J. Farcy , Ilhyun Kim , Prakash Math , Matthew Merten , Vijaykumar Kadgi
发明人： Martin G. Dixon , Ravi Rajwar , Konrad K. Lai , Robert S. Chappell , Rajesh S. Parthasarathy , Alexandre J. Farcy , Ilhyun Kim , Prakash Math , Matthew Merten , Vijaykumar Kadgi
IPC分类号： G06F9/52 , G06F12/08 , G06F12/10 , G06F9/30
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/3859 , G06F9/3861 , G06F9/467 , G06F9/528 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0895 , G06F12/0897 , G06F12/1027 , G06F12/1045 , G06F13/1673 , G06F13/4068 , G06F13/4282 , G06F2212/452 , G06F2212/50 , G06F2212/60 , G06F2212/602 , G06F2212/621 , G06F2212/68 , G06F2212/682
摘要： An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

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