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61. 发明申请

US20080197495A1 STRUCTURE FOR REDUCING LATERAL FRINGE CAPACITANCE IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于减少半导体器件中的侧向电容的结构
公开(公告)号：US20080197495A1
公开(公告)日：2008-08-21
申请号：US12106396
申请日：2008-04-21
申请人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca , Vidhya Ramachandran , Theodorus E. Standaert
发明人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca , Vidhya Ramachandran , Theodorus E. Standaert
IPC分类号： H01L23/48
CPC分类号： H01L21/76834 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.
摘要翻译：半导体结构包括形成在层间电介质（ILD）层内的多个导电线和形成在ILD层和导电线之上的非平面覆盖层，其中覆盖层相对于导电线在第导线。

62. 发明授权

US07355271B2 Flexible assembly of stacked chips 有权
标题翻译：堆叠芯片的灵活组装
公开(公告)号：US07355271B2
公开(公告)日：2008-04-08
申请号：US10573561
申请日：2003-09-30
申请人： Richard P. Volant , Kevin S. Petrarca , George F. Walker
发明人： Richard P. Volant , Kevin S. Petrarca , George F. Walker
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L21/568 , H01L21/6835 , H01L23/5387 , H01L24/24 , H01L24/82 , H01L25/0652 , H01L25/50 , H01L2221/68359 , H01L2221/68372 , H01L2224/04042 , H01L2224/04105 , H01L2224/05554 , H01L2224/18 , H01L2224/24137 , H01L2224/48091 , H01L2224/48227 , H01L2224/49431 , H01L2224/49433 , H01L2224/73209 , H01L2224/73259 , H01L2224/73267 , H01L2224/82005 , H01L2224/9222 , H01L2225/06524 , H01L2225/06527 , H01L2225/06579 , H01L2225/06589 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/3511 , H01L2924/00014 , H01L2924/00
摘要： A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip (130) is provided with additional interconnect wiring to a substrate (500), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.
摘要翻译：描述了由多个折叠集成电路芯片（100,110,120）组成的三维封装，其中至少一个芯片提供用于与堆叠的附加芯片的电连接的互连路径，并且至少一个芯片（130）是提供与衬底（500），封装或印刷电路板的附加互连布线。进一步描述的是提供互连芯片的柔性布置的方法，其被折叠成三维布置以在安装在基板，二级封装或印刷电路板上时消耗较少的空中空间。

63. 发明授权

US07279426B2 Like integrated circuit devices with different depth 有权
标题翻译：像具有不同深度的集成电路器件
公开(公告)号：US07279426B2
公开(公告)日：2007-10-09
申请号：US11162766
申请日：2005-09-22
申请人： Habib Hichri , Kimberly A. Larsen , Helen L. Maynard , Kevin S. Petrarca
发明人： Habib Hichri , Kimberly A. Larsen , Helen L. Maynard , Kevin S. Petrarca
IPC分类号： H01L21/302
CPC分类号： H01L21/02118 , H01F41/041 , H01L21/02282 , H01L21/3083 , H01L21/312 , H01L21/76816 , H01L23/522 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth of the cavities formed in the areas with vias will extend deeper into the substrate than the cavities formed in areas without vias. Such occurs because the polymer deposits unevenly along the surface of the substrate and more specifically, more thinly in areas with underlying depressions. Once filled with a conductive material, cavities which extend more deeply into the substrate, which were formed in areas with vias, become inductors, and the cavities which extend less deeply into the substrate, which were formed in areas without vias, become interconnects.
摘要翻译：本发明同时形成了类似结构和不同深度的集成电路器件，例如互连和电感器。本发明通过具有通孔和没有通孔的区域的衬底上的区域上沉积保形聚合物。同时，在具有和不具有通孔的区域中形成空腔。在具有通孔的区域中形成的空腔的深度将比在没有通孔的区域中形成的空腔更深地延伸到基底中。这是因为聚合物沿着衬底的表面不均匀地沉积，更具体地，在具有基底凹陷的区域中更薄。一旦填充有导电材料，形成在具有通孔的区域中更深地延伸到衬底中的空腔成为电感器，并且在没有通孔的区域中形成的不太深地延伸到衬底中的空穴变成互连。

64. 发明授权

US07068138B2 High Q factor integrated circuit inductor 有权
标题翻译：高Q系列集成电路电感
公开(公告)号：US07068138B2
公开(公告)日：2006-06-27
申请号：US10768773
申请日：2004-01-29
申请人： Daniel C. Edelstein , Panayotis C. Andricacos , John M. Cotte , Hariklia Deligianni , John H. Magerlein , Kevin S. Petrarca , Kenneth J. Stein , Richard P. Volant
发明人： Daniel C. Edelstein , Panayotis C. Andricacos , John M. Cotte , Hariklia Deligianni , John H. Magerlein , Kevin S. Petrarca , Kenneth J. Stein , Richard P. Volant
IPC分类号： H01F27/24
CPC分类号： H01L24/12 , H01L23/5227 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L27/08 , H01L28/10 , H01L2224/0401 , H01L2224/04042 , H01L2224/05007 , H01L2224/05014 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05084 , H01L2224/05555 , H01L2224/05557 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/48744 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19042 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： An inductor and a method of forming and the inductor, the method including: (a) providing a semiconductor substrate; (b) forming a dielectric layer on a top surface of the substrate; (c) forming a lower trench in the dielectric layer; (d) forming a resist layer on a top surface of the dielectric layer; (e) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (f) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.
摘要翻译：一种电感器及其形成方法和电感器，所述方法包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成电介质层; （c）在介电层中形成下沟槽; （d）在介电层的顶表面上形成抗蚀剂层; （e）在所述抗蚀剂层中形成上沟槽，所述上沟槽对准所述下沟槽，所述上沟槽的底部通向所述下沟槽; 和（f）用导体完全填充下沟槽至少部分地填充上沟槽，以形成电感器。所述电感器包括顶表面，底表面和侧壁，所述电感器的下部将固定距离延伸到形成在半导体衬底上的电介质层和在所述电介质层上方延伸的上部; 以及用于电接触所述电感器的装置。

65. 发明授权

US07053460B2 Multi-level RF passive device 有权
公开(公告)号：US07053460B2
公开(公告)日：2006-05-30
申请号：US10026146
申请日：2001-12-21
申请人： Richard P. Volant , Seshadri Subbanna , Robert A. Groves , John C. Malinowski , Kenneth J. Stein , Kevin S. Petrarca
发明人： Richard P. Volant , Seshadri Subbanna , Robert A. Groves , John C. Malinowski , Kenneth J. Stein , Kevin S. Petrarca
IPC分类号： H01L29/00 , H01L23/48
CPC分类号： H01L23/66 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A passive electrical device includes a first electrical conductor, a second electrical conductor disposed over the first conductor; and a third electrical conductor connecting the first conductor to the second conductor. The said first, second and third conductors are disposed on a semiconductor substrate. The sheet resistivity of the first conductor is approximately equal to the sheet resistivity of the second conductor.

66. 发明授权

US06992368B2 Production of metal insulator metal (MIM) structures using anodizing process 有权
公开(公告)号：US06992368B2
公开(公告)日：2006-01-31
申请号：US10422794
申请日：2003-04-25
申请人： Richard P. Volant , John M. Cotte , Kevin S. Petrarca , Kenneth J. Stein
发明人： Richard P. Volant , John M. Cotte , Kevin S. Petrarca , Kenneth J. Stein
IPC分类号： H01L21/8238
CPC分类号： H01L28/40 , H01L21/31687 , Y10S438/957
摘要： Metal-insulator-metal capacitor structures are formed in semiconductor substrates using an anodization procedure on deposited underlying metalization followed by deposition of the second metal and planarization by chemical-mechanical polishing or other procedures. The process is additive in character, as opposed to traditional subtractive etch processes for forming capacitor structures. In addition, the process can be used in damascene applications, and can be used to form a wide variety of capacitive structures while reducing the number of mask layers required for formation.

67. 发明授权

US06924185B2 Fuse structure and method to form the same 失效
标题翻译：保险丝结构和方法形成相同
公开(公告)号：US06924185B2
公开(公告)日：2005-08-02
申请号：US10680618
申请日：2003-10-07
申请人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
发明人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
IPC分类号： H01L23/525 , H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.
摘要翻译：用于熔丝结构的方法和结构包括绝缘体层，穿过绝缘体层延伸到下面的布线层的多个熔丝电极，连接到电极的电镀熔丝元件和界面壁。保险丝元件位于绝缘体的外部，并且在绝缘体和保险丝元件之间并置有间隙。界面壁还包括第一侧壁，第二侧壁和内壁，其中内壁设置在间隙内。熔丝电极彼此直径相对，并且熔丝元件垂直地设置在熔丝电极的上方。保险丝元件是电镀，无电镀，或是超薄保险丝。

68. 发明授权

US06873027B2 Encapsulated energy-dissipative fuse for integrated circuits and method of making the same 失效
标题翻译：用于集成电路的封装式耗能型熔断器及其制造方法
公开(公告)号：US06873027B2
公开(公告)日：2005-03-29
申请号：US10002447
申请日：2001-10-26
申请人： Timothy J. Dalton , Kevin S. Petrarca , Richard P. Volant
发明人： Timothy J. Dalton , Kevin S. Petrarca , Richard P. Volant
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A laser-programmable fuse structure for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the fuse structure includes a conductive layer, the conductive layer completing a conductive path between wiring segments in a wiring layer. An organic material is encapsulated underneath the conductive layer, wherein the fuse structure is blown open by application of a beam of laser energy thereto.
摘要翻译：公开了一种用于集成电路器件的激光可编程熔丝结构。在本发明的示例性实施例中，熔丝结构包括导电层，导电层在布线层中的布线段之间完成导电路径。有机材料被封装在导电层下面，其中通过向其施加激光能量而将熔丝结构吹开。

69. 发明授权

US06635506B2 Method of fabricating micro-electromechanical switches on CMOS compatible substrates 有权
标题翻译：在CMOS兼容基板上制造微机电开关的方法
公开(公告)号：US06635506B2
公开(公告)日：2003-10-21
申请号：US10014660
申请日：2001-11-07
申请人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
发明人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
IPC分类号： H01L2100
CPC分类号： B81C1/00246 , B81B2201/016 , B81B2201/018 , B81B2203/0127 , B81B2207/07 , B81C1/00611 , B81C2201/0122 , B81C2203/0735 , H01G5/40 , H01H59/0009
摘要： A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.
摘要翻译：描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。然后用牺牲脱模材料填充空腔。然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。

70. 发明授权

US06448629B2 Semiconductor device and method of making same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06448629B2
公开(公告)日：2002-09-10
申请号：US09354742
申请日：1999-07-29
申请人： Rebecca D. Mih , Kevin S. Petrarca
发明人： Rebecca D. Mih , Kevin S. Petrarca
IPC分类号： H01L2906
CPC分类号： H01L21/0332 , H01L21/76224 , H01L21/7684
摘要： A second or cap dielectric layer is interposed between the usual or base dielectric layer and the metallic circuitry layer of a semiconductor device. The base dielectric layer has a plurality of recesses in an inactive part of the semiconductor device into which parts of the cap dielectric layer extend to interlock the cap dielectric layer to the base dielectric layer and to oppose shearing or tearing of the either (1) the metallic circuitry layer as the metallic circuitry layer is subjected to chemical-mechanical polishing, or (2) a hard mask layer from the base dielectric layer as the metallic circuitry layer is subjected to chemical-mechanical polishing.
摘要翻译：第二或盖电介质层介于通常的或基底电介质层与半导体器件的金属电路层之间。基极电介质层在半导体器件的非活性部分中具有多个凹部，盖电介质层的部分延伸以将盖电介质层与基底电介质层互锁，并且相对于（1）的剪切或撕裂金属电路层作为金属电路层进行化学机械抛光，或（2）当金属电路层进行化学机械抛光时，从基极介电层获得硬掩模层。

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