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    • 61. 发明授权
    • Printing apparatus for printing of quarter em-size
    • 用于打印四分之一尺寸的打印设备
    • US5579448A
    • 1996-11-26
    • US191078
    • 1994-02-04
    • Ichiro Yamamoto
    • Ichiro Yamamoto
    • B41J2/485B41J5/30G06F3/12G06K15/02G06K15/00
    • G06K15/02G06K2215/0057G06K2215/0062
    • According to a printing apparatus of the invention, for a printing operation of print data of special size which is transmitted from a host computer, when any quarter em-size letter is contained in the print data, it is judged whether font data of half resolution exists. If the font data of half resolution exists, the font data of half resolution is read out, and a quarter em-size letter is printed on the basis of the read-out font data. On the other hand, if no font data of half resolution exists, font data for the quarter em-size letter is prepared on the basis of the font data of special resolution and printed. Therefore, quarter em-size letters can be printed with high quality.
    • 根据本发明的打印装置,对于从主计算机发送的特殊大小的打印数据的打印操作,当打印数据中包含任何四分之一尺寸的字母时,判断是否具有半分辨率的字体数据 存在 如果存在半分辨率的字体数据,则读出半分辨率的字体数据,并且基于读出的字体数据打印四分之一尺寸的字母。 另一方面,如果不存在半分辨率的字体数据,则基于特殊分辨率的字体数据来准备用于四分之一尺寸字母的字体数据并打印。 因此,可以高质量打印四分之一尺寸的字母。
    • 62. 发明授权
    • Clock supply circuit layout in a circuit area
    • 时钟供电电路布局在电路区域
    • US5270592A
    • 1993-12-14
    • US933345
    • 1992-08-21
    • Tadao TakahashiIchiro YamamotoHiroyuki Fukuyama
    • Tadao TakahashiIchiro YamamotoHiroyuki Fukuyama
    • H01L21/82G06F1/10H01L21/822H01L23/522H01L27/04H03K19/00H03K21/02H03K19/01H03K5/13
    • H01L23/5222G06F1/10H01L2924/0002
    • A clock supply circuit having a circuit area includes an input terminal for receiving a clock pulse and a buffer having an input electrically connected to the input terminal and an output. The buffer is disposed in the center of the circuit area. The clock supply circuit also includes a main conductive pattern electrically connected to the output of the buffer. The main conductive pattern is disposed through the center of the circuit area. Each of the branch conductive patterns is electrically connected to the main conductive pattern and extends from the main conductive pattern. Also, each of the branch conductive patterns has a width smaller than the width of the main conductive pattern. Each of the clock receiving circuits is electrically connected to one of the branch conductive patterns and disposed in the circuit area. The number of the clock receiving circuits electrically connected to one branch conductive pattern is same.
    • 具有电路区域的时钟供给电路包括用于接收时钟脉冲的输入端子和具有电连接到输入端子的输入端和输出端的缓冲器。 缓冲器设置在电路区域的中心。 时钟供给电路还包括电连接到缓冲器的输出的主导电图案。 主导电图案通过电路区域的中心布置。 每个分支导电图案电连接到主导电图案并且从主导电图案延伸。 此外,每个分支导电图案的宽度小于主导电图案的宽度。 每个时钟接收电路电连接到一个分支导电图案并且设置在电路区域中。 电连接到一个分支导电图案的时钟接收电路的数量相同。
    • 65. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07595538B2
    • 2009-09-29
    • US11205141
    • 2005-08-17
    • Ichiro Yamamoto
    • Ichiro Yamamoto
    • H01L29/72
    • H01L29/518H01L21/28185H01L21/28194H01L21/28202H01L21/823857H01L29/513H01L29/78
    • A P-type MOSFET 120 includes a semiconductor substrate (N-well 102b); a gate insulating film formed on the semiconductor substrate, composed of a high-dielectric-constant film 108 which contains a silicate compound containing a first element selected from the group consisting of Hf, Zr and any of lanthanoids, together with N; a gate electrode formed on the gate insulating film, and is configured by a polysilicon film 114 containing a P-type impurity; and a blocking oxide film 110 formed between the gate insulating film and the gate electrode, blocking a reaction between the first element and the polysilicon film 114, and having a relative dielectric constant of 8 or above.
    • P型MOSFET120包括半导体衬底(N阱102b); 形成在半导体衬底上的栅极绝缘膜,由含有选自Hf,Zr和任何镧系元素的第一元素的硅酸盐化合物与N的高介电常数膜108组成; 形成在栅极绝缘膜上的栅电极,由包含P型杂质的多晶硅膜114构成; 以及形成在栅极绝缘膜和栅电极之间的阻挡氧化膜110,阻挡第一元件和多晶硅膜114之间的反应,并且具有8或更高的相对介电常数。
    • 66. 发明申请
    • White light-emitting organic electroluminescence (EL) device and method of adjusting chromaticity of the device
    • 白色发光有机电致发光(EL)装置及其调节色度的方法
    • US20090079338A1
    • 2009-03-26
    • US12221763
    • 2008-08-05
    • Kenji MoriIchiro YamamotoTakanori Murasaki
    • Kenji MoriIchiro YamamotoTakanori Murasaki
    • H01J1/62
    • H01L51/5036H01L51/5016
    • The white light-emitting organic EL device of the present invention comprises: an anode, a cathode, at least a red light-emitting layer, a blue light-emitting layer and a green light-emitting layer provided between the anode and the cathode, and an intermediate layer between any two adjacent layers of the respective light-emitting layers, wherein, when CIE chromaticity coordinates of a dopant incorporated into the red light-emitting layer are represented by (xR, yR), CIE chromaticity coordinates of a dopant incorporated into the blue light-emitting layer are represented by (xB, yB), CIE chromaticity coordinates of a dopant incorporated into the green light-emitting layer are represented by (xG, yG), and target CIE chromaticity coordinates of white light emitted from the device are represented by (xt, yt), Δy represented as a difference between yR and yB, and Δx represented as a difference between xG and xt satisfy the following relationships: Δy≦0.18 Δx≦0.10.
    • 本发明的白色发光有机EL元件包括阳极,阴极,至少红色发光层,蓝色发光层和设置在阳极和阴极之间的绿色发光层, 以及在各发光层的任意两个相邻层之间的中间层,其中当掺入到红色发光层中的掺杂剂的CIE色度坐标由(xR,yR)表示时,掺杂掺杂的CIE色度坐标 通过(xB,yB)表示蓝色发光层,掺入到绿色发光层中的掺杂剂的CIE色度坐标由(xG,yG)表示,并且由(xG,yG)表示的白色光的目标CIE色度坐标 器件由(xt,yt)表示,Deltay表示为yR和yB之间的差,表示为xG和xt之间的差的Deltax满足以下关系:<?in-line-formula description =“In- 行公式“end =”lead“?> Deltay <= 0.18 <?in-line-formula description =”In-line Formulas“end =”tail“?> <?in-line-formula description =”内联公式 “end =”lead“?> Deltax <= 0.10。<?in-line-formula description =”In-line Formulas“end =”tail“?>
    • 68. 发明授权
    • Semiconductor device and method for manufacturing same
    • 半导体装置及其制造方法
    • US07446059B2
    • 2008-11-04
    • US11180648
    • 2005-07-14
    • Ichiro Yamamoto
    • Ichiro Yamamoto
    • H01L21/31H01L21/469
    • H01L29/517H01L21/28176H01L21/28194H01L21/314H01L21/3142H01L21/31616H01L21/31645H01L28/56H01L29/513
    • A semiconductor device is provided which is capable of improving its reliability by using a material having a high relative dielectric constant as a material for its gate insulating film, by suppressing degradation of an EOT (Equivalent Oxide Thickness) and by preventing crystallization of the material having a high relative dielectric constant. The semiconductor device (Field Effect Transistor) has a silicon substrate, a seed layer made up of silicon oxide, a gate insulating film made of amorphous hafnium aliminate and a gate electrode made up of polycrystalline silicon formed the gate insulating film. The gate insulating film is so formed that a hafnium concentration decreases monotonously or step by step, whereas an aluminum concentration increases monotonously or step by step along a direction of a thickness of the gate insulating film from the silicon substrate side toward the gate electrode. In a boundary region between a lower layer side region and an upper layer side region in the gate insulating film, the hafnium and aluminum concentrations change continuously.
    • 提供一种半导体器件,其能够通过使用具有高相对介电常数的材料作为其栅极绝缘膜的材料来提高其可靠性,通过抑制EOT(等效氧化物厚度)的劣化,并且通过防止具有 高相对介电常数。 半导体器件(场效应晶体管)具有硅衬底,由氧化硅构成的种子层,由无定形铪合金构成的栅极绝缘膜和由多晶硅构成的栅电极形成栅极绝缘膜。 栅极绝缘膜形成为使得铪浓度单调或逐步降低,而铝浓度沿着栅极绝缘膜的厚度从硅衬底侧朝向栅电极单调或逐步增加。 在栅绝缘膜的下层侧区域和上层侧区域之间的边界区域中,铪和铝的浓度连续变化。