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61. 发明授权

US07398522B2 Compilation and runtime information generation and optimization 有权
标题翻译：编译和运行时信息的生成和优化
公开(公告)号：US07398522B2
公开(公告)日：2008-07-08
申请号：US10797800
申请日：2004-03-10
申请人： Hideaki Komatsu , Toshio Suganuma , Toshiaki Yasue
发明人： Hideaki Komatsu , Toshio Suganuma , Toshiaki Yasue
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： To collect frequencies with which processes of a program are executed at high speed. A compiler apparatus for optimizing a program based on frequencies with which each process is executed has a loop process detection portion for detecting a repeatedly executed loop process of the program, a loop process frequency collection portion for collecting loop process frequencies with which the loop process is executed in the program, an in-loop process frequency collection portion for collecting in-loop process frequencies with which, as against times of execution of loop process, each of a plurality of in-loop processes included in the loop process is executed, an in-loop execution information generating portion for generating in-loop execution information indicating the frequencies with which each of the plurality of in-loop processes is executed in the case where the program is executed, and an optimization portion for optimizing the program based on the in-loop execution information.
摘要翻译：收集高速执行程序进程的频率。一种用于基于执行每个处理的频率对程序进行优化的编译装置，具有循环处理检测部分，用于检测程序的重复执行的循环处理;循环处理频率收集部分，用于收集循环处理频率在程序中执行的循环过程频率收集部分，用于收集循环处理频率，与执行循环处理的次数相比，执行循环处理中包括的多个循环中的每个处理，执行循环执行信息生成部分，用于在执行程序的情况下，生成指示执行多个循环中每个处理的频率的循环执行信息;以及优化部分，用于基于循环执行信息。

62. 发明授权

US07383544B2 Compiler device, method, program and recording medium 失效
标题翻译：编译器装置，方法，程序和记录介质
公开(公告)号：US07383544B2
公开(公告)日：2008-06-03
申请号：US10793370
申请日：2004-03-04
申请人： Motohiro Kawahito , Hideaki Komatsu
发明人： Motohiro Kawahito , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/41
摘要： Compiler device optimizes a program by changing an order of executing instructions. The device includes: a replaceability determination unit which determines whether a first instruction included in a first instruction sequence and a second instruction included in a second instruction sequence executed after the first instruction sequence can be replaced with a common processing instruction group including a common processing instruction for processing at least respective parts of processings by the first and second instructions together; a common processing instruction group generation unit which generates a common processing instruction group in the first instruction sequence, in place of the first instruction, when the replaceability determination unit determines the first and second instructions to be replaceable; and an instruction insertion unit which inserts the second instruction into a third instruction sequence that is an instruction sequence other than the first instruction sequence and is executed before the second instruction sequence.
摘要翻译：编译器设备通过更改执行指令的顺序来优化程序。该装置包括：可替换性确定单元，其确定包括在第一指令序列中的第一指令和包括在第一指令序列之后执行的第二指令序列中的第二指令是否可以被包括公共处理指令的公共处理指令组替换用于通过第一和第二指令一起处理至少相应的处理部分; 当可替换性确定单元确定可替换的第一和第二指令时，代替第一指令，生成第一指令序列中的公共处理指令组的公共处理指令组生成单元; 以及指令插入单元，其将第二指令插入作为第一指令序列以外的指令序列的第三指令序列，并且在第二指令序列之前执行。

63. 发明申请

US20070156685A1 Method for sorting data using SIMD instructions 审中-公开
标题翻译：使用SIMD指令排序数据的方法
公开(公告)号：US20070156685A1
公开(公告)日：2007-07-05
申请号：US11320095
申请日：2005-12-28
申请人： Hiroshi Inoue , Takao Moriyama , Hideaki Komatsu
发明人： Hiroshi Inoue , Takao Moriyama , Hideaki Komatsu
IPC分类号： G06F7/00
CPC分类号： G06F7/36
摘要： A method and apparatus are provided to perform fast data sorting by using SIMD instruction. Data comparison and swapping is executed with SIMD instructions in parallel and without conditional branching.
摘要翻译：提供了一种通过使用SIMD指令执行快速数据排序的方法和装置。使用SIMD指令并行执行数据比较和交换，无条件分支。

64. 发明申请

US20060095902A1 Information processing device and compiler 审中-公开
公开(公告)号：US20060095902A1
公开(公告)日：2006-05-04
申请号：US11255027
申请日：2005-10-20
申请人： Takuya Nakaike , Hideaki Komatsu , Seiichi Kawano
发明人： Takuya Nakaike , Hideaki Komatsu , Seiichi Kawano
IPC分类号： G06F9/45
CPC分类号： G06F1/3203 , G06F8/4432 , G06F9/4893 , Y02D10/24 , Y02D10/41
摘要： Devices, compilers and methods to reduce energy consumption associated with execution of a program by adjusting a computational capability of a CPU with higher accuracy than before. A device sets an appropriate computational capability to the CPU. It includes: changing a computational capability of the CPU every time each of a plurality of program areas included in the execution program is executed while the execution program is being executed, and measuring execution time each of the program areas; deciding an optimal computational capability required to execute the program area using the CPU, based on the execution time for each of the computational capabilities measured for the respective program areas; and performing setting of the optimal computational capability for executing the program area, which is to be used when executing the program area again in the course of executing the execution program, for each of the program areas.

65. 发明申请

US20050268293A1 Compiler optimization 失效
标题翻译：编译器优化
公开(公告)号：US20050268293A1
公开(公告)日：2005-12-01
申请号：US11133897
申请日：2005-05-20
申请人： Motohiro Kawahito , Hideaki Komatsu
发明人： Motohiro Kawahito , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/4434
摘要： Provides effective use of architecture-specific instructions. There is provided a compiler including: a target partial program detecting unit for detecting, from among a partial programs of the program to be optimized, a partial program including instructions corresponding to all instructions included in the pattern to be replaced as a partial program to be optimized; an instruction sequence transforming unit for transforming, in the partial program to be optimized, instructions other than those instructions corresponding to instructions included in the pattern to be replaced and those instructions having execution dependencies different from the pattern to be replaced, so that dependencies between instructions included in the partial program to be optimized match the pattern to be replaced; an instruction sequence replacing unit for replacing the partial program to be optimized transformed by the instruction sequence transforming unit with a target instruction sequence determined in accordance with the pattern to be replaced.
摘要翻译：提供针对特定于架构的指令的有效使用。提供了一种编译器，其包括：目标部分程序检测单元，用于从要优化的程序的部分程序中检测包括与要替换的模式中包括的所有指令相对应的指令作为部分程序的部分程序，优化; 指令序列变换单元，用于在要优化的部分程序中转换除了与要替换的模式中包括的指令相对应的指令以及具有与要替换的模式不同的执行依赖性的指令之外的指令，使得指令之间的依赖性包括在要优化的部分程序中匹配待更换的模式; 指令序列替换单元，用于将由指令序列变换单元变换的要优化的部分程序替换为根据要替换的模式确定的目标指令序列。

66. 发明授权

US06931635B2 Program optimization 失效
标题翻译：程序优化
公开(公告)号：US06931635B2
公开(公告)日：2005-08-16
申请号：US10020656
申请日：2001-10-29
申请人： Tatsushi Inagaki , Hideaki Komatsu
发明人： Tatsushi Inagaki , Hideaki Komatsu
IPC分类号： G06F9/38 , G06F9/45
CPC分类号： G06F8/445
摘要： A program optimization method for converting program source code written in a programming language into machine language includes steps of: analyzing a target program and detecting an exception generative instruction, which may generate an exception, and exception generation detection instructions, which brunches a process to an exception process when an exception occurrence condition is detected and an exception has occurred. The method also includes steps of dividing the exception generation detection instructions into first instructions, for the detection of exception occurrence conditions, and into second instructions, for branching processes to the exception process when the exception occurrence conditions are detected; and establishing dependencies among program instructions, so that when one of the exception occurrence conditions is detected the process is shifted from a first instruction to a second instruction, and so that when none of the exception occurrence conditions are detected, the process is shifted from a first instruction to an exception generative instruction.
摘要翻译：一种用于将以编程语言编写的程序源代码转换为机器语言的程序优化方法，包括以下步骤：分析目标程序并检测可能产生异常的异常生成指令，以及将进程冲突到检测到异常发生条件并发生异常时的异常处理。该方法还包括以下步骤：将异常生成检测指令划分为用于检测异常发生状况的第一指令，以及当检测到异常发生条件时将异常处理分支到第二指令中的步骤; 并且在程序指令之间建立相关性，使得当检测到异常发生状况之一时，处理从第一指令移位到第二指令，并且当没有检测到异常发生条件时，处理从第一条指令给异常生成指令。

67. 发明授权

US06253372B1 Determining a communication schedule between processors 失效
标题翻译：确定处理器之间的通信时间表
公开(公告)号：US06253372B1
公开(公告)日：2001-06-26
申请号：US09361316
申请日：1999-07-27
申请人： Hideaki Komatsu , Takeshi Ogasawara
发明人： Hideaki Komatsu , Takeshi Ogasawara
IPC分类号： G06F945
CPC分类号： G06F15/17368
摘要： To generate an optimum communication schedule when data is transmitted or received between processors which constitute a parallel computer or a distributed multiprocessor system. Processors which each perform inter-processor communication are sorted into a plurality of groups. A communication graph is generated whose nodes correspond to the groups and edges correspond to the communications. Communication graphs are generated for distances between nodes from one through N−1. Each communication graph corresponds to a communication step of the inter-processor communication. Communication is grasped as a whole by the communication graph and the edge of the communication graph means the inter-processor communication which is performed in a certain communication step. In this way, the communication can be optimized.
摘要翻译：当在构成并行计算机或分布式多处理器系统的处理器之间发送或接收数据时，生成最佳通信调度。每个进行处理器间通信的处理器分为多个组。生成其节点对应于组和边缘对应于通信的通信图。生成从1到N-1的节点之间的距离的通信图。每个通信图对应于处理器间通信的通信步骤。通过通信图来整体地进行通信，通信图的边缘是指在某个通信步骤中执行的处理器间通信。以这种方式，可以优化通信。

68. 发明授权

US06173562B1 Exhaust recirculation type combined plant 失效
标题翻译：排气再循环型联合厂房
公开(公告)号：US06173562B1
公开(公告)日：2001-01-16
申请号：US09022441
申请日：1998-02-12
申请人： Motoaki Utamura , Shinichi Hoizumi , Yasushi Takeda , Toshihiko Sasaki , Hideaki Komatsu , Seiichi Kirikami , Takeshi Suzumura , Tetsuo Sasada , Takashi Ikeguchi , Shigehisa Sugita
发明人： Motoaki Utamura , Shinichi Hoizumi , Yasushi Takeda , Toshihiko Sasaki , Hideaki Komatsu , Seiichi Kirikami , Takeshi Suzumura , Tetsuo Sasada , Takashi Ikeguchi , Shigehisa Sugita
IPC分类号： F02C618
CPC分类号： F02C9/20 , F01K23/101 , F02C1/007 , F02C3/34 , F02C6/18 , F02C7/10 , F02C9/16 , F05D2220/72 , Y02E20/16
摘要： To improve the thermal efficiency when an exhaust heat recovery type combined cycle plant having a gas turbine and a steam turbine in combination is operated at a partial load, the gas turbine exhaust is recirculated and returned to the compressor, and the combustion temperature is prevented from being lowered at the partial load. Preferably, the temperature is maintained constant. In this way, the thermal efficiency during operation at partial load can be improved.
摘要翻译：为了在具有燃气轮机和蒸汽轮机组合的排气热回收型联合循环装置以部分负荷运转的情况下提高热效率，燃气轮机排气再循环并返回到压缩机，并且防止燃烧温度在部分负载下降低。优选地，温度保持恒定。以这种方式，可以提高在部分负荷下操作期间的热效率。

69. 发明授权

US5625832A Distributed processing control method and distributed processing system 失效
标题翻译：分布式处理控制方法和分布式处理系统
公开(公告)号：US5625832A
公开(公告)日：1997-04-29
申请号：US388534
申请日：1995-02-14
申请人： Gyo Ohsawa , Hideaki Komatsu
发明人： Gyo Ohsawa , Hideaki Komatsu
IPC分类号： G06F15/16 , G06F9/44 , G06F9/45 , G06F9/46 , G06F15/177 , G06F13/00
CPC分类号： G06F8/45
摘要： A distributed control method and distributed processing system to decrease data communication overhead and to execute a program efficiently. One of processors at which data arrives in a multiprocessing system is selected by a polling process (310 to 312). All data which arrives at the selected processor is received therefrom to fill a control table of sending and receiving data and a control table of calculation sets with marks for indicating the completion of data receipt (314 to 316). Data to be sent is sent so that the control table of sending and receiving data is marked to indicate the completion of data sending (318 to 320). If data has not yet arrived during polling, required data is sent to all processors (322). The execution of actual calculations using array processes is effected by using calculation sets such that the control table of calculation sets is marked indicating the completion of calculation. This is repeated until all calculation sets are received and there are none present indicating that the calculation not been completed thereby indicating that "the execution of calculation is completed" (324 to 328).
摘要翻译：一种分布式控制方法和分布式处理系统，用于降低数据通信开销并有效执行程序。通过轮询处理（310〜312）选择数据到达多处理系统的处理器之一。接收到所选处理器的所有数据，以填充发送和接收数据的控制表以及用于指示数据接收完成的标记的计算集合的控制表（314至316）。发送要发送的数据，使得发送和接收数据的控制表被标记以指示数据发送的完成（318至320）。如果在轮询期间尚未到达数据，则将所需数据发送到所有处理器（322）。通过使用计算集来实现使用数组处理的实际计算的执行，使得计算集合的控制表被标记指示计算的完成。重复这一操作，直到接收到所有计算集，并且没有表示计算未完成，从而指示“计算的执行完成”（324至328）。

70. 发明授权

US08769547B2 Reduced data transfer during processor context switching 有权
标题翻译：在处理器上下文切换期间减少数据传输
公开(公告)号：US08769547B2
公开(公告)日：2014-07-01
申请号：US13563713
申请日：2012-07-31
申请人： Hiroshi Inoue , Moriyoshi Ohara , Takao Moriyama , Yukihiko Sohda , Hideaki Komatsu
发明人： Hiroshi Inoue , Moriyoshi Ohara , Takao Moriyama , Yukihiko Sohda , Hideaki Komatsu
IPC分类号： G06F9/46
CPC分类号： G06F9/462
摘要： Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.
摘要翻译：处理器上下文切换期间的数据传输减少，特别是在分时微任务编程模型方面。在将具有本地存储器的处理器从第一处理切换到第二处理之前，确定不需要传送到系统存储器以适当地保存与第一处理相关联的数据的本地存储器的一部分。然后，处理器的上下文从第一处理切换到第二处理，包括将与第一处理相关联的所有本地存储器传送到系统存储器 - 除了被确定为不是的本地存储器的部分之外需要保存到系统存储器以适当地保存与第一进程相关联的数据。因此，将上下文从第一处理切换到第二处理导致从本地存储器传送到系统存储器的数据的减少。

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