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    • 61. 发明授权
    • Digital broadcast receiver and digital broadcast receiving method
    • 数字广播接收机和数字广播接收方式
    • US07260158B2
    • 2007-08-21
    • US10398943
    • 2001-09-25
    • Kenichi ShiraishiAkihiro Horii
    • Kenichi ShiraishiAkihiro Horii
    • H03K9/00H04L27/06H04L27/14H04L27/22
    • H04H60/32H04H60/12H04N21/434H04N21/4345H04N21/4382H04N21/4621
    • A digital broadcast receiver capable of adequately receiving a higher-level layer service along with a lower-level layer service even if the reception CNR degrades. A demodulation decoding section (2) of the receiver judges on the basis of transport and multiplexing configuration control information whether the TS packet allocated to each slot is adapted to a higher-level layer service or a lower-level layer service and informs a code writing section (3) of the result. The code writing section (3) writes, in each TS packet, a layer identification code for judging whether the TS packet is adapted to a higher-level layer service or a lower-layer service and synthesizes a resultant TS packet. A stream separating section (4) reads the layer identification code along with the PID in the packet header included in the TS packet and finds and extracts a desired TS packet.
    • 即使接收CNR劣化,能够适当地接收更高级别的层服务以及较低层次的服务的数字广播接收机。 接收机的解调解码部分(2)根据传输和多路复用配置控制信息判断分配给每个时隙的TS分组是否适合于较高级别的层服务或较低层服务,并通知代码写入 第(3)节结果。 代码写入部分(3)在每个TS分组中写入一个层识别码,用于判断TS分组是适应于较高级别的服务还是适用于较低层服务,并且合成所产生的TS分组。 流分离部分(4)在TS分组中包含的分组报头中读取与PID一起的层识别码,并发现并提取期望的TS分组。
    • 62. 发明授权
    • Apparatus and method for receiving BS digital broadcast
    • 用于接收BS数字广播的装置和方法
    • US07221719B2
    • 2007-05-22
    • US10031085
    • 2001-05-17
    • Kenichi ShiraishiShoji MatsudaAkihiro Horii
    • Kenichi ShiraishiShoji MatsudaAkihiro Horii
    • H04L27/14
    • H04L27/2273H04L27/0012H04L2027/0053H04L2027/0057H04L2027/0067H04L2027/0069
    • An improved apparatus for receiving BS digital broadcast is disclosed. The apparatus for receiving BS digital broadcast of the present invention has first to third filters and a selective complex calculator circuit.Each of the first to third filters 18 to 20 identifies the modulation technique applied to the received signal, by the modulation identification signals A0, A1 received from a timing generator circuit 25, and filters a phase error signal PED according to the identified modulation technique. The selective complex calculator circuit 21 shifts the phase of a signal point indicated by an I signal ADI1 and a Q signal ADQ1 absolute-phased by an absolute-phasing section 14, by a phase corresponding to the phase error signal filtered by the first to third filters 18 to 20. At this moment, the selective complex calculator circuit 21 selects the phase error signal corresponding to the modulation technique identified from the modulation identification signals A0, A1 received from the timing generator circuit 25. Consequently, in the burst receiving, it is possible to reduce the effect on the error rate because of the signal noise of the ODU to a degree equal to that in the continuous receiving.
    • 公开了一种用于接收BS数字广播的改进的装置。 本发明的用于接收BS数字广播的装置具有第一至第三滤波器和选择性复合计算器电路。 第一至第三滤波器18至20中的每一个通过从定时发生器电路25接收的调制识别信号A 0,A 1识别应用于接收信号的调制技术,并根据所识别的调制对相位误差信号PED进行滤波 技术。 选择复合计算器电路21将由由绝对定相部分14绝对相位的I信号ADI 1和Q信号ADQ 1指示的信号点的相位移位相应于由第一 到第三过滤器18至20。 此时,选择性复数计算器电路21选择与从定时发生器电路25接收的调制识别信号A 0,A 1识别的调制技术相对应的相位误差信号。 因此,在脉冲串接收中,由于ODU的信号噪声等于连续接收的信号噪声,可以降低对误码率的影响。
    • 65. 发明授权
    • Method and circuit for acquisition
    • 采集方法和电路
    • US07079597B1
    • 2006-07-18
    • US10049808
    • 2000-10-02
    • Kenichi ShiraishiAkihiro HoriiShoji Matsuda
    • Kenichi ShiraishiAkihiro HoriiShoji Matsuda
    • H04L27/16H04L7/00H04J3/06
    • H04L7/042H04L27/22H04L2027/003H04L2027/0057H04L2027/0065H04L2027/0067
    • Frame synchronization is quickly established to acquire an RF channel in a short time. Numerically controlled oscillators 1-1 to 1-3, complex calculation circuits 2-1 to 2-3, band limit filters 3-1 to 3-3, a selector 7, a phase error detection circuit 9, a loop filter 10, and an AFC circuit 11 compose a carrier regeneration loop for removing the frequency error of the carrier included in an in-phase component I and a quadrant component Q of the baseband signal input to the complex calculation circuits 2-1 to 2-3. A timing generator 6 detects which of frame synchronization pattern detection circuits 5-1 to 5-3 has detected a frame synchronization pattern, provides the selector 7 with a selection signal corresponding to the decision result, and sends a switch signal to the AFC circuit 11. Thereafter, the carrier for removing the frequency error included in the baseband signal is regenerated to acquire an RF channel in a short time.
    • 快速建立帧同步,以在短时间内获取RF信道。 数字控制振荡器1-1-1-3,复数计算电路2-1-2-3,频带限制滤波器3-1至3-3,选择器7,相位误差检测电路9,环路滤波器10和 AFC电路11构成用于去除包括在同相分量I中的载波的频率误差的载波再生回路和输入到复数计算电路2-1至2-3的基带信号的象限分量Q。 定时发生器6检测哪个帧同步模式检测电路5-1至5-3已经检测到帧同步模式,向选择器7提供与该决定结果相对应的选择信号,并向AFC电路11发送开关信号 。 此后,重新生成用于消除基带信号中包括的频率误差的载波,以在短时间内获取RF信道。
    • 68. 发明授权
    • Circuit for detecting the phase of received signal
    • 用于检测接收信号相位的电路
    • US06690745B1
    • 2004-02-10
    • US09463233
    • 2000-01-21
    • Akihiro HoriiKenichi Shiraishi
    • Akihiro HoriiKenichi Shiraishi
    • H04L2706
    • H04L27/2332H04L2027/0065
    • A received signal phase detecting circuit in provided in which the circuit scale is small. The circuit functions so as to capture a frame synchronizing signal from a demodulated baseband signal, extract a symbol stream during the period of frame synchronizing signal from the demodulated baseband signal through delay circuits (41, 42) at a timing matching the bit stream of the captured synchronizing signal, rotating the phase of a corresponding symbol extracted from the symbol stream when the big in the bit in the bit stream is logic “0” by 80°, outputting the symbol after the phase rotation and a corresponding symbol extracted from the symbol stream when the bit in the bit stream is logic “1” from a 0°/180° phase rotating circuit (43), operating the cumulative average of the output from the 0°/180° phase rotating circuit (43) for a specific period through cumulative averaging circuits (45, 46), rotating the phase of the outputs therefrom through a 22.5° phase rotating circuit (48), and determining the phase of the output therefrom by a phase determining circuit (49).
    • 一种接收信号相位检测电路,其中电路规模小。 电路起作用以从解调的基带信号中捕获帧同步信号,在帧同步信号的周期期间,通过延迟电路(41,42),在与 捕获的同步信号,当比特流中的比特中的大比特是逻辑“0”80°时,旋转从符号流提取的对应符号的相位,在相位旋转之后输出符号,并从符号中提取相应的符号 当位流中的位是从0°/ 180°相位旋转电路(43)的逻辑“1”时,对来自0°/ 180°相位旋转电路(43)的输出的累积平均值进行特定操作 通过累积平均电路(45,46),通过22.5°相位旋转电路(48)旋转其输出的相位,并且通过相位确定电路(49)确定其输出的相位。
    • 69. 发明授权
    • Absolute-phasing synchronization capturing circuit
    • 绝对定相同步捕捉电路
    • US06678342B1
    • 2004-01-13
    • US09446460
    • 1999-12-22
    • Akihiro HoriiKenichi Shiraishi
    • Akihiro HoriiKenichi Shiraishi
    • H04L704
    • H04L27/2273H04L27/22H04L27/2332H04L2027/0046H04L2027/0067
    • A small-scale absolute-phasing synchronization capturing circuit for absolute phasing of a received signal by selectively transmitting a baseband signal demodulated through a demodulator (1), a baseband signal subjected to phase rotation through a remapper (11), a baseband signal output from a first inverting means, a baseband signal output from a second inverting means based on the phase angle of the received signal relative to the phase rotation of the transmission signal. The most significant bit in the demodulated baseband signal and the most significant bit in the baseband signal subjected to phase rotation through the remapper (11) are extracted and a frame synchronization signal is captured according to the extracted significant bit.
    • 一种用于通过选择性地发送通过解调器(1)解调的基带信号,通过再映射器(11)进行相位旋转的基带信号,从基站信号输出的基带信号,用于绝对定相接收信号的小型绝对定相同步捕获电路 第一反相装置,基于接收信号相对于发送信号的相位旋转的相位角从第二反相装置输出的基带信号。 解调的基带信号中的最高有效位和通过再映射器(11)进行相位旋转的基带信号中的最高有效位被提取,并且根据提取的有效位捕获帧同步信号。