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    • 62. 发明申请
    • STATISTICAL METHOD FOR HIERARCHICALLY ROUTING LAYOUT UTILIZING FLAT ROUTE INFORMATION
    • 使用平坦路径信息进行层次分层布局的统计方法
    • US20120110536A1
    • 2012-05-03
    • US12912819
    • 2010-10-27
    • Vikas AgarwalYonatan MittlefehldtJafar Nahidi
    • Vikas AgarwalYonatan MittlefehldtJafar Nahidi
    • G06F17/50
    • G06F17/5077
    • An integrated circuit design is routed by first creating temporary routes in a flattened layout, generating blockage information for sub-blocks in the layout based on the temporary routes, and establishing a routing order for cells using a depth-first search. Cells in the original layout are then routed according to the routing order using the blockage information. The temporary routes are sorted into internal routes, terminal routes, and spanning routes. Blockage information for each sub-block includes a first cellview equal to the internal routes, a second cellview equal to the terminal routes plus the spanning routes, and a third cellview equal to the total tracks in the sub-block minus the first and second cellviews. The invention is particularly suited for routing a hierarchical integrated circuit design. By examining the complete hierarchy, the invention ensures that enough metal will be remaining at upper level sub-blocks to complete the routing automatically.
    • 通过首先在平坦化布局中创建临时路由来路由集成电路设计,基于临时路由生成布局中的子块的阻塞信息,以及使用深度优先搜索来建立小区的路由顺序。 然后使用阻塞信息,根据路由顺序路由原始布局中的单元。 临时路由分为内部路由,终端路由和跨越路由。 每个子块的阻塞信息包括等于内部路由的第一小区视图,等于终端路由加上跨越路由的第二小区视图,以及等于子块中的总轨迹的第三小区视图减去第一和第二小区视图 。 本发明特别适用于布线分级集成电路设计。 通过检查完整的层次结构,本发明确保在上级子块中剩余足够的金属以自动完成路由。
    • 67. 发明授权
    • Energy-saving circuit and method using charge equalization across complementary nodes
    • 节能电路和方法在互补节点上使用电荷均衡
    • US07545176B2
    • 2009-06-09
    • US11923714
    • 2007-10-25
    • Vikas AgarwalSanjay DubeySaiful IslamGaurav Mittal
    • Vikas AgarwalSanjay DubeySaiful IslamGaurav Mittal
    • H03K19/0175H03K19/094
    • H03K5/151H03K19/0008
    • An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states.
    • 在互补节点上使用电荷均衡的节能电路和方法降低存储器电路和其它电路中的功耗,例如具有互补高电容节点的宽多路复用器。 改变检测电路检测要施加到位线的状态变化,并且如果要施加状态改变则产生脉冲。 连接在节点之间的通过门被响应于脉冲激活以均衡位线上的电荷。 驱动电路使能输入也被延迟,使得位线不被驱动,直到电荷被均衡并且通路禁止。 在一个实施例中,驱动器电路仅通过变化检测器的脉冲输出暂时使能,并且使用保持器电路将位线保持在其断言状态。
    • 69. 发明申请
    • ENERGY-SAVING CIRCUIT AND METHOD USING CHARGE EQUALIZATION ACROSS COMPLEMENTARY NODES
    • 节能电路和使用充电均衡的方法
    • US20090108920A1
    • 2009-04-30
    • US11923714
    • 2007-10-25
    • Vikas AgarwalSanjay DubeySaiful IslamGaurav Mittal
    • Vikas AgarwalSanjay DubeySaiful IslamGaurav Mittal
    • G05F1/10
    • H03K5/151H03K19/0008
    • An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states.
    • 在互补节点上使用电荷均衡的节能电路和方法降低存储器电路和其它电路中的功耗,例如具有互补高电容节点的宽多路复用器。 改变检测电路检测要施加到位线的状态变化,并且如果要施加状态改变则产生脉冲。 连接在节点之间的通过门被响应于脉冲激活以均衡位线上的电荷。 驱动电路使能输入也被延迟,使得位线不被驱动,直到电荷被均衡并且通路禁止。 在一个实施例中,驱动器电路仅通过变化检测器的脉冲输出暂时使能,并且使用保持器电路将位线保持在其断言状态。
    • 70. 发明授权
    • System and method for collection, aggregation, and composition of metrics
    • 用于收集,聚合和组合度量的系统和方法
    • US07509414B2
    • 2009-03-24
    • US10976941
    • 2004-10-29
    • Vikas AgarwalWilliam P. HornArun Kumar
    • Vikas AgarwalWilliam P. HornArun Kumar
    • G06F15/173
    • G06Q30/02G06F9/546
    • A method for collecting, aggregating, and composing metrics and a computer system comprises a producer application adapted to periodically generate metrics comprising state information of the producer application; a metric engine adapted to aggregate the metrics; and a consumer application adapted to receive the aggregated metrics, wherein the metric engine is further adapted to produce new metrics in accordance with desired requirements of the consumer application. The computer system further comprises a metric service policy adapted to provide definitions of the metrics generated from the producer application and desired requirements of the consumer application, wherein the metric service policy is adapted to establish an executable set of actions for producing the new metrics from the generated metrics, wherein the metric service policy is adapted to be executable by the metric engine, and wherein multiple metric service policies are simultaneously executable by the metric engine.
    • 用于收集,聚合和组合度量的方法以及计算机系统包括适于周期性地生成包括生产者应用的状态信息的度量的生成器应用; 适于聚合度量的度量引擎; 以及适于接收所述聚合度量的消费者应用,其中所述度量引擎还适于根据所述消费者应用的期望要求产生新的度量。 计算机系统还包括适于提供从生产者应用程序产生的度量的定义和消费者应用程序的期望需求的度量服务策略,其中度量服务策略适于建立可执行的一组动作,用于从 其中所述度量服务策略适于由所述度量引擎执行,并且其中多个度量服务策略可由所述度量引擎同时执行。