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    • 65. 发明授权
    • Semiconductor memory cell having information storage transistor and
switching transistor
    • 具有信息存储晶体管和开关晶体管的半导体存储单元
    • US5428238A
    • 1995-06-27
    • US164812
    • 1993-12-10
    • Yutaka HayashiTakeshi Matsushita
    • Yutaka HayashiTakeshi Matsushita
    • G11C11/405G11C11/404H01L21/8238H01L21/8242H01L27/092H01L27/108H01L29/786H01L27/02H01L27/01H01L29/00
    • H01L27/108G11C11/404
    • A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.l and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub. 2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.
    • 提供了一种结构的半导体存储单元或用于ASIC的半导体存储单元,其确保稳定的晶体管操作,其不需要常规DRAM中所需的大容量电容器,这确保可靠地读取和写入信息,这允许 短通道设计,并且可以减小单元格区域。 半导体存储单元包括:包括半导体沟道层Ch1,第一和第二导电栅极G1,G2以及第一和第二导电层L1,L2的信息存储晶体管TR1; 以及包括半导体沟道形成区域Ch2,第三导电栅极G3以及第三和第四导电层L3,L4的开关晶体管TR2,其中第四导电层L4连接到第二导电栅极G2,第一导电栅极G1和 第三导电栅极G3连接到第一存储单元选择线,第一导电层L1和第三导电层L3连接到第二存储单元选择线,第二导电层L 2连接到 固定电位,并且半导体沟道形成区域Ch2连接到读/写选择线。
    • 70. 发明授权
    • Data processing system for determining min/max in a single operation
cycle as a result of a single instruction
    • 数据处理系统,用于根据单个指令在单个操作周期内确定最小/最大值
    • US4774688A
    • 1988-09-27
    • US786997
    • 1985-10-15
    • Makoto KobayashiAkihiro KurodaTakeshi Matsushita
    • Makoto KobayashiAkihiro KurodaTakeshi Matsushita
    • G06F7/02G06F7/22G06F7/544G06F7/57G06F9/30G06F9/302G06F9/00
    • G06F7/57G06F7/22G06F7/544G06F9/3001G06F9/30021
    • A data processing system is provided which includes ALU data busses, temporary operand storage registers, an accumulator, and a set of latches for temporarily storing data to be supplied to the input of the ALU. Output multiplexer is provided which can select the output of one of the latches or that of the ALU which is sent to the accumulator. A detector is also provided for determining whether the smaller or larger one of two data elements is stored in said latches according to the status of the ALU and a new MIN/MAX instruction and the selected data element is returned to a predetermined temporary storage register via the output multiplexer. A controller operates in cooperation with the system instruction decoder to effect this operation with a single machine instruction. In determining the minimum or maximum of N data elements, it is only necessary to execute the MIN or MAX operations N-1 times, whereby the maximum or the minimum can be easily determined, the length of the program shortened, and the execution time reduced.
    • 提供了一种数据处理系统,其包括ALU数据总线,临时操作数存储寄存器,累加器和用于临时存储要提供给ALU的输入的数据的一组锁存器。 提供输出多路复用器,可以选择锁存器中的一个或发送到累加器的ALU的输出。 还提供一种检测器,用于根据ALU的状态和新的MIN / MAX指令确定两个数据元素中较小或更大的数据元素是否被存储在所述锁存器中,并且所选择的数据元素经由 输出多路复用器。 控制器与系统指令解码器协同操作,以通过单个机器指令来实现该操作。 在确定N个数据元素的最小值或最大值时,仅需要执行MIN或MAX次操作N-1次,从而可以容易地确定最大值或最小值,缩短程序长度,缩短执行时间 。