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61. 发明授权

US09317360B2 Machine check summary register 有权
标题翻译：机器检查摘要寄存器
公开(公告)号：US09317360B2
公开(公告)日：2016-04-19
申请号：US13995458
申请日：2011-12-29
申请人： Jose A. Vargas , Mohan J. Kumar , James B. Crossland , Murugasamy K. Nachimuthu , Theodros Yigzaw
发明人： Jose A. Vargas , Mohan J. Kumar , James B. Crossland , Murugasamy K. Nachimuthu , Theodros Yigzaw
IPC分类号： G06F11/00 , G06F11/08 , G06F11/22 , G06F11/10 , G06F11/07
CPC分类号： G06F11/1004 , G06F11/0724 , G06F11/0793
摘要： In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.
摘要翻译：在一些实现中，处理器可以包括具有多个错误报告寄存器的机器检查架构，其能够接收用于机器检查错误的数据。总结寄存器可以包括多个可设置位置，每个位置可以代表错误报告寄存器中的至少一个。可以将汇总寄存器中的一个或多个可设置位置设置为指示一个或多个错误报告寄存器是否保持机器检查错误的数据。因此，当发生机器检查错误时，可以访问总结寄存器以识别处理器视图中的任何错误报告寄存器是否包含有效的错误数据，而不是在处理器视图中读取每个错误报告寄存器。

62. 发明授权

US09311138B2 System management interrupt handling for multi-core processors 有权
标题翻译：多核处理器的系统管理中断处理
公开(公告)号：US09311138B2
公开(公告)日：2016-04-12
申请号：US13799327
申请日：2013-03-13
申请人： Sarathy Jayakumar , Mohan J. Kumar , Michael D. Kinney
发明人： Sarathy Jayakumar , Mohan J. Kumar , Michael D. Kinney
IPC分类号： G06F9/48 , G06F11/07
CPC分类号： G06F9/4812 , G06F11/0772
摘要： Technologies for system management interrupt (“SMI”) handling include a number of processor cores configured to enter a system management mode (“SMM”) in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed.
摘要翻译：用于系统管理中断（“SMI”）处理的技术包括配置为响应于检测到SMI而进入系统管理模式（“SMM”）的多个处理器核心。进入SMM并获取主线程锁的第一个处理器核心设置正在进行的标志，并执行主SMI处理程序，而不必等待其他处理器内核进入SMM。其他处理器核心执行从属SMI处理程序。主SMI处理程序可以指示下级SMI处理程序来处理核心特定的SMI。响应于检测到由获取主线程锁的处理器核心清除的SMI，多核处理器可以设置SMI服务挂起标志。进入SMM的处理器核心在确定进行中标志未被设置并且未设置服务暂挂标志时，可以立即恢复正常执行，以检测和减轻假SMI。描述和要求保护其他实施例。

63. 发明授权

US09202015B2 Entering a secured computing environment using multiple authenticated code modules 有权
标题翻译：使用多个经过身份验证的代码模块进入安全的计算环境
公开(公告)号：US09202015B2
公开(公告)日：2015-12-01
申请号：US12650579
申请日：2009-12-31
申请人： Sham M. Datta , Ernie F. Brickell , Mohan J. Kumar
发明人： Sham M. Datta , Ernie F. Brickell , Mohan J. Kumar
IPC分类号： G06F21/00 , G06F21/57 , G06F21/71
CPC分类号： G06F21/00 , G06F21/57 , G06F21/572 , G06F21/71 , G06F2221/2149 , G06F2221/2153
摘要： Systems, apparatuses, and methods, and for entering a secured system environment using multiple authenticated code modules are disclosed. In one embodiment, a processor includes a decoder and control logic. The decoder is to decode a secured enter instruction. The control logic is to find an entry corresponding to the processor in a match table in a master authenticated code module and to read a master header and an individual authenticated code module from the master authenticated code module in response to decoding the secured enter instruction.
摘要翻译：公开了系统，装置和方法以及使用多个认证代码模块输入安全系统环境。在一个实施例中，处理器包括解码器和控制逻辑。解码器是对安全的输入指令进行解码。控制逻辑是在主认证代码模块的匹配表中找到与处理器相对应的条目，并且响应于对安全的进入指令进行解码，从主认证代码模块读取主标题和单独的认证代码模块。

64. 发明授权

US08973094B2 Execution of a secured environment initialization instruction on a point-to-point interconnect system 有权
标题翻译：在点对点互连系统上执行安全环境初始化指令
公开(公告)号：US08973094B2
公开(公告)日：2015-03-03
申请号：US11442230
申请日：2006-05-26
申请人： Shamanna M Datta , Mohan J Kumar
发明人： Shamanna M Datta , Mohan J Kumar
IPC分类号： H04L9/32 , G06F21/00 , G06F21/53 , G06F21/74
CPC分类号： G06F21/53 , G06F21/00 , G06F21/74 , G06F21/85
摘要： Methods and apparatus for initiating secure operations in a microprocessor system are described. In one embodiment, a system includes a processor to execute a secured enter instruction, and a chipset to cause the system to enter a quiescent state during execution of the secured enter instruction.
摘要翻译：描述了在微处理器系统中启动安全操作的方法和装置。在一个实施例中，系统包括执行安全输入指令的处理器和芯片组，以使系统在执行安全输入指令期间进入静止状态。

65. 发明申请

US20140188829A1 TECHNOLOGIES FOR PROVIDING DEFERRED ERROR RECORDS TO AN ERROR HANDLER 审中-公开
标题翻译：将提示错误记录提供给错误处理的技术
公开(公告)号：US20140188829A1
公开(公告)日：2014-07-03
申请号：US13728451
申请日：2012-12-27
申请人： Narayan Ranganathan , Mahesh Natu , Mohan J. Kumar , Sarathy Jayakumar
发明人： Narayan Ranganathan , Mahesh Natu , Mohan J. Kumar , Sarathy Jayakumar
IPC分类号： G06F17/30
CPC分类号： G06F16/21
摘要： Technologies to generate an error record are described herein. A method includes performing a scan of one or more error logs to identify a source of data in response to an attempt to access the data, determining whether an amount of time to complete the scan will exceed a threshold value, and generating a notice that the error record will be deferred based on the determination. A system includes a data collector to scan one or more error logs to identify a source of data in response to an attempt to access the data, a controller to determine whether an amount of time to scan the error logs to identify the source of data will exceed a threshold value, and a signal generator to generate a signal indicating that the error record is to be deferred based on the determination.
摘要翻译：本文描述了生成错误记录的技术。一种方法包括：响应于访问数据的尝试，执行一个或多个错误日志的扫描以识别数据源，确定完成扫描的时间量是否将超过阈值，以及生成通知错误记录将根据确定推迟。系统包括数据收集器，用于扫描一个或多个错误日志以响应于访问数据的尝试来识别数据源;控制器，用于确定扫描错误日志以识别数据源的时间量是否将超过阈值，以及信号发生器，用于基于该确定产生指示错误记录被延迟的信号。

66. 发明申请

US20130212406A1 TECHNIQUE FOR PROVIDING SECURE FIRMWARE 审中-公开
标题翻译：提供安全固件的技术
公开(公告)号：US20130212406A1
公开(公告)日：2013-08-15
申请号：US13837640
申请日：2013-03-15
申请人： Shamanna M. Datta , Mohan J. Kumar
发明人： Shamanna M. Datta , Mohan J. Kumar
IPC分类号： G06F21/60
CPC分类号： G06F21/60 , G06F21/57
摘要： A technique to verify firmware. One embodiment of the invention uses a processor's micro-code to verify a system's firmware, such that the firmware can be included in a trusted chain of code along with the operating system.
摘要翻译：验证固件的技术。本发明的一个实施例使用处理器的微代码来验证系统的固件，使得固件可以与操作系统一起被包括在可信赖的代码链中。

67. 发明授权

US08473945B2 Enabling system management mode in a secure system 有权
标题翻译：在安全系统中启用系统管理模式
公开(公告)号：US08473945B2
公开(公告)日：2013-06-25
申请号：US11967779
申请日：2007-12-31
申请人： Sham M. Datta , Mohan J. Kumar , Maheeh Natu
发明人： Sham M. Datta , Mohan J. Kumar , Maheeh Natu
IPC分类号： G06F9/455
CPC分类号： G06F9/30087 , G06F9/45533
摘要： Apparatuses, methods, and systems for enabling system management mode in a secure system are disclosed. In one embodiment, a processor includes sub-operating-system mode logic, virtual machine logic, and control logic. The sub-operating-system mode logic is to support a sub-operating-system mode. The virtual machine logic is to support virtualization. The control logic is to prevent virtualization from being enabled when the sub-operating-system mode is disabled.
摘要翻译：公开了一种用于在安全系统中启用系统管理模式的装置，方法和系统。在一个实施例中，处理器包括子操作系统模式逻辑，虚拟机逻辑和控制逻辑。子操作系统模式逻辑是支持子操作系统模式。虚拟机逻辑是支持虚拟化。控制逻辑是防止在禁用子操作系统模式时启用虚拟化。

68. 发明授权

US08429418B2 Technique for providing secure firmware 有权
标题翻译：提供安全固件的技术
公开(公告)号：US08429418B2
公开(公告)日：2013-04-23
申请号：US11355697
申请日：2006-02-15
申请人： Shamanna M. Datta , Mohan J. Kumar
发明人： Shamanna M. Datta , Mohan J. Kumar
IPC分类号： G06F21/00
CPC分类号： G06F21/60 , G06F21/57
摘要： A technique to verify firmware. One embodiment of the invention uses a processor's micro-code to verify a system's firmware, such that the firmware can be included in a trusted chain of code along with the operating system.
摘要翻译：验证固件的技术。本发明的一个实施例使用处理器的微代码来验证系统的固件，使得固件可以与操作系统一起被包括在可信赖的代码链中。

69. 发明申请

US20110179311A1 INJECTING ERROR AND/OR MIGRATING MEMORY IN A COMPUTING SYSTEM 审中-公开
标题翻译：在计算机系统中注入错误和/或移植存储器
公开(公告)号：US20110179311A1
公开(公告)日：2011-07-21
申请号：US12971868
申请日：2010-12-17
申请人： Murugasamy K. Nachimuthu , Mohan J. Kumar , Sarathy Jayakumar , Chung-Chi Wang
发明人： Murugasamy K. Nachimuthu , Mohan J. Kumar , Sarathy Jayakumar , Chung-Chi Wang
IPC分类号： G06F11/00
CPC分类号： G06F11/3676
摘要： In some embodiments a request is received to perform an error injection or a memory migration, a mode is entered that blocks requests from agents other than a current processor core or thread, the error is injected or the memory is migrated, and the mode that blocks requests from the agents other than the current processor core or thread is exited. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，接收到执行错误注入或存储器迁移的请求，输入阻止来自除当前处理器核心或线程以外的代理的请求的模式，注入错误或存储器迁移的模式以及阻止来自除当前处理器核心或线程之外的代理的请求退出。描述和要求保护其他实施例。

70. 发明申请

US20110055469A1 Providing State Storage In A Processor For System Management Mode 有权
标题翻译：在系统管理模式的处理器中提供状态存储
公开(公告)号：US20110055469A1
公开(公告)日：2011-03-03
申请号：US12550737
申请日：2009-08-31
申请人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
发明人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
IPC分类号： G06F12/06
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
摘要： In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态管理模式（SMM）。以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。描述和要求保护其他实施例。

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