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61. 发明申请

US20080109697A1 Memory and method for checking reading errors thereof 有权
标题翻译：用于检查读取错误的存储器和方法
公开(公告)号：US20080109697A1
公开(公告)日：2008-05-08
申请号：US11727256
申请日：2007-03-26
申请人： Wen-Chiao Ho , Chin-Hung Chang , Chun-Hsiung Hung , Kuen-Long Chang
发明人： Wen-Chiao Ho , Chin-Hung Chang , Chun-Hsiung Hung , Kuen-Long Chang
IPC分类号： H03M13/00
CPC分类号： H03M13/13 , G06F11/1068 , H03M13/03 , H03M13/3776
摘要： A method for checking reading errors of a memory includes receiving a first data fragment and accordingly generating a first ECC and a first count index; writing the first data fragment, the first ECC and the first count index into a memory; reading the first data fragment from the memory as a second data fragment, generating a second ECC and second count index according to the second data fragment; determining whether the first count index and second count index are equal; determining whether the first ECC and the second ECC are equal; and outputting the second data fragment when the first count index is equal to the second count index and the first ECC is equal to the second ECC.
摘要翻译：用于检查存储器的读取错误的方法包括接收第一数据片段并相应地生成第一ECC和第一计数索引; 将第一数据片段，第一ECC和第一计数索引写入存储器; 从所述存储器读取所述第一数据片段作为第二数据片段，根据所述第二数据片段生成第二ECC和第二计数索引; 确定第一计数指数和第二计数指数是否相等; 确定第一ECC和第二ECC是否相等; 并且当所述第一计数索引等于所述第二计数索引并且所述第一ECC等于所述第二ECC时，输出所述第二数据片段。

62. 发明授权

US07180780B1 Multi-level-cell programming methods of non-volatile memories 有权
标题翻译：非易失性存储器的多级单元编程方法
公开(公告)号：US07180780B1
公开(公告)日：2007-02-20
申请号：US11281181
申请日：2005-11-17
申请人： Wen Chiao Ho , Chin Hung Chang , Kuen Long Chang , Chun Hsiung Hung
发明人： Wen Chiao Ho , Chin Hung Chang , Kuen Long Chang , Chun Hsiung Hung
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/12 , G11C11/5671 , G11C16/0475 , G11C16/3459
摘要： The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance. In a first embodiment, the present invention programs the multi-level cell in a multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a first program level (level1) and a second program level (level2) to level 1, and programming the second program level from the first program level. In a second embodiment, the present invention programs the multi-level cell in the multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a second program level (level2), and programming a first program level (level 1).
摘要翻译：本发明提供了一种在氮化物俘获存储器单元的多位单元中改变多电平单元编程的顺序的新颖方法，其减少或消除了程序步骤之间的电压阈值偏移，同时避免了在读取窗口由互补位干扰引起。在第一实施例中，本发明按照以下顺序在具有四位的多位单元中编程多电平单元：编程第三程序级（level3），编程第一程序级（level1）和第二程序级别（level2）到级别1，并从第一程序级别编程第二程序级别。在第二实施例中，本发明按照以下顺序对具有四位的多比特单元中的多电平单元进行编程：编程第三程序级（level3），编程第二程序级（level2），并编程第一程序级（1级）。

63. 发明授权

US06255900B1 Rapid on chip voltage generation for low power integrated circuits 有权
标题翻译：用于低功率集成电路的快速片上电压产生
公开(公告)号：US06255900B1
公开(公告)日：2001-07-03
申请号：US09284435
申请日：1999-04-12
申请人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , Tien-Shin Ho , I-Long Lee , Tzeng-Hei Shiau , Ray-Lin Wan
发明人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , Tien-Shin Ho , I-Long Lee , Tzeng-Hei Shiau , Ray-Lin Wan
IPC分类号： G05F110
CPC分类号： G11C16/30 , G05F3/242 , G11C5/145 , G11C16/08 , H02M3/07
摘要： An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which in response to the transition boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit. The detection circuit signals the voltage boost circuit when the node reaches the first threshold, and signals the voltage boost circuit when the node reaches the second threshold. According to one aspect of the invention, the first threshold is reached within less than 5 nanoseconds, and more preferably about 2 nanoseconds, or less, of the transition in the boost signal.
摘要翻译：提供了适用于具有低电源电压（例如，2.7至3.6伏特）的闪存器件的集成电路的片上电压产生电路。电压升压电路耦合到电源电压输入和升压信号，该升压信号响应于升压信号的转变而升高集成电路上的节点上的片内电压。升压电路具有第一模式，其响应于转换而以第一升压速率提升片上电压直到第一阈值，并且响应于转换的第二模式将片上电压提升到第二阈值升压速率直到第二个阈值。优选系统中的第二次升压速度比第一次升压速率慢。检测电路耦合到接收片上电压的集成电路上的节点和电压升压电路。当节点达到第一阈值时，检测电路向升压电路发信号，当节点达到第二阈值时，信号通知升压电路。根据本发明的一个方面，在升压信号中的转变的小于5纳秒，更优选约2纳秒或更小的范围内达到第一阈值。

64. 发明授权

US08825978B2 Memory apparatus 有权
标题翻译：存储设备
公开(公告)号：US08825978B2
公开(公告)日：2014-09-02
申请号：US13584393
申请日：2012-08-13
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
IPC分类号： G06F12/00 , G06F13/42 , G11C29/00
CPC分类号： G11C7/1072 , G11C7/1066 , G11C7/222 , G11C2207/104
摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.
摘要翻译：存储装置包括主机装置和从装置。主机设备存储验证数据。从设备包括存储单元，控制单元和逻辑单元。控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。前导码数据和存储数据根据内部时钟信号发送。主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

65. 发明授权

US08743638B2 Method and circuit for testing a multi-chip package 有权
标题翻译：用于测试多芯片封装的方法和电路
公开(公告)号：US08743638B2
公开(公告)日：2014-06-03
申请号：US13564189
申请日：2012-08-01
申请人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
发明人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
IPC分类号： G11C7/00
CPC分类号： G11C29/10 , G11C29/12005
摘要： A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.
摘要翻译：提供了一种用于测试多芯片封装的方法和电路。多芯片封装至少包括存储器芯片，并且存储器芯片包括多个存储器单元。该方法包括对存储器单元执行正常读取操作，以检查从存储器单元读取的数据是否与存储器单元中的预置数据相同; 以及对所述存储器单元执行特殊读取操作，以检查从所述存储器单元读取的数据是否与期望值相同，其中所述期望值与存储在所述存储器单元中的数据无关。

66. 发明授权

US08599640B2 Method and apparatus of addressing a memory integrated circuit 有权
标题翻译：寻址存储器集成电路的方法和装置
公开(公告)号：US08599640B2
公开(公告)日：2013-12-03
申请号：US13708150
申请日：2012-12-07
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Hsieh Ming Chih
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Hsieh Ming Chih
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12
摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.
摘要翻译：存储器集成电路具有访问存储器集成电路的存储单元的控制电路。控制电路响应于包括第一命令和第二命令的命令。第一个命令指定高位地址位集合。第二个命令指定低位地址位集合。地址位的高位集合和地址位的低位集合构成存储器集成电路的完整访问地址。第一个命令和第二个命令在命令代码中有所不同。

67. 发明申请

US20130279265A1 Method and Apparatus for Reducing Erase Time of Memory By Using Partial Pre-Programming 有权
标题翻译：通过部分预编程减少存储器擦除时间的方法和装置
公开(公告)号：US20130279265A1
公开(公告)日：2013-10-24
申请号：US13453312
申请日：2012-04-23
申请人： Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C16/16 , G11C16/344
摘要： Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.
摘要翻译：非易失性存储器阵列的存储单元的特征在于包括至少一个擦除的阈值电压范围和编程的阈值电压范围的多个阈值电压范围之一。响应于擦除非易失性存储器阵列的一组存储单元的擦除命令，执行至少包括预编程相位和擦除阶段的多个相位。预编程相位对组内的阈值电压中的第一组存储器单元进行编程，并且不对组中擦除的阈值电压范围内的阈值电压的组中的第二组存储器单元进行编程。通过不对第二组存储器单元进行编程，如果第二组存储器单元与第一组存储器单元一起被编程，那么执行预编程相位更快。

68. 发明授权

US08547755B2 Method and apparatus of performing an erase operation on a memory integrated circuit 有权
标题翻译：在存储器集成电路上执行擦除操作的方法和装置
公开(公告)号：US08547755B2
公开(公告)日：2013-10-01
申请号：US13708102
申请日：2012-12-07
申请人： Yi-Fan Chang , Cheng Ming Yih , Su-chueh Lo , Jian Shing Liu , Kuen Long Chang , Chun-Hsiung Hung
发明人： Yi-Fan Chang , Cheng Ming Yih , Su-chueh Lo , Jian Shing Liu , Kuen Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/14 , G11C16/344 , G11C16/3477
摘要： Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.
摘要翻译：各种讨论的方法包括在擦除验证和擦除擦除操作的子操作期间改进擦除组的边缘字线和中心字线的分组。在另一种方法中，改变边缘字线的电压电平以解决擦除组的过擦除问题，并且还提高擦除时间性能。另一种方法使用虚拟字线。

69. 发明授权

US08542536B2 System and method for detecting disturbed memory cells of a semiconductor memory device 有权
标题翻译：用于检测半导体存储器件的干扰存储单元的系统和方法
公开(公告)号：US08542536B2
公开(公告)日：2013-09-24
申请号：US13539831
申请日：2012-07-02
申请人： Chun-Hsiung Hung , Jeng-Kuan Lin , Kuen-Long Chang
发明人： Chun-Hsiung Hung , Jeng-Kuan Lin , Kuen-Long Chang
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/28
摘要： A method of detecting a disturb condition of a memory cell includes application of multiple sets of conditions to the memory cell and determining whether the memory cell behaves as a programmed memory cell in response to the sets of conditions. A disturbed memory cell can be detected if the memory cell responds as a programmed memory cell in response to one of the sets of conditions, but responds as an erased memory cell in response to another of the sets of conditions.
摘要翻译：一种检测存储器单元的干扰状况的方法包括将多组条件应用于存储单元，并根据条件集确定存储单元是否作为编程存储器单元。如果存储器单元响应于一组条件而作为编程存储器单元进行响应，则可以检测到干扰的存储器单元，而是响应于另一组条件而被响应为擦除存储器单元。

70. 发明授权

US08411509B2 Memory and method for charging a word line thereof 有权
公开(公告)号：US08411509B2
公开(公告)日：2013-04-02
申请号：US11976975
申请日：2007-10-30
申请人： Chun-Yi Lee , Yung-Feng Lin , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Chun-Yi Lee , Yung-Feng Lin , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C8/14 , G11C16/08
摘要： A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage.

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