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61. 发明授权

US07675773B2 Semiconductor memory, test method of semiconductor memory and system 失效
标题翻译：半导体存储器，半导体存储器和系统的测试方法
公开(公告)号：US07675773B2
公开(公告)日：2010-03-09
申请号：US12130480
申请日：2008-05-30
申请人： Kaoru Mori , Toshikazu Nakamura , Jun Ohno , Masaki Okuda
发明人： Kaoru Mori , Toshikazu Nakamura , Jun Ohno , Masaki Okuda
IPC分类号： G11C11/34
CPC分类号： G11C8/18 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C29/1201 , G11C29/18 , G11C29/48 , G11C2029/1802
摘要： An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced.
摘要翻译：地址开关电路接收提供给第一地址端子组的行地址信号和提供给第二地址端子组的列地址信号。此外，地址开关电路接收提供给第二地址端子组的行地址信号，然后接收提供给第二地址端子组的列地址信号，并将接收到的行地址信号和接收的列地址信号提供给行解码器，列解码器在第二操作模式期间。可以通过在第二操作模式中执行半导体存储器的操作测试来增加一次测试的半导体存储器的数量。此外，可以使用用于其他半导体存储器的测试资产来测试半导体存储器。因此，可以提高测试效率，并且可以降低测试成本。

62. 发明授权

US07652941B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07652941B2
公开(公告)日：2010-01-26
申请号：US12133890
申请日：2008-06-05
申请人： Kaoru Mori , Shinya Fujioka
发明人： Kaoru Mori , Shinya Fujioka
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C5/147 , G11C11/4094 , G11C29/02 , G11C29/025 , G11C29/12005 , G11C2029/5006 , G11C2211/4065 , G11C2211/4067
摘要： A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status.
摘要翻译：提供了一种存储器件，其具有：用于存储数据的存储器单元; 一个字线选择存储单元; 可选择的存储单元的位线; 预充电电源，用于向位线提供预充电电压; 预充电电路，用于将预充电电源连接到或从所述位线断开; 以及电流限制元件，用于根据操作状态至少两步地控制在预充电电源和位线之间流动的电流的大小。

63. 发明授权

US07583553B2 Semiconductor memory and refresh cycle control method 有权
标题翻译：半导体存储器和刷新周期控制方法
公开(公告)号：US07583553B2
公开(公告)日：2009-09-01
申请号：US11797817
申请日：2007-05-08
申请人： Kaoru Mori
发明人： Kaoru Mori
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/04 , G11C11/401 , G11C11/40626 , G11C29/02 , G11C29/028 , G11C2029/0409 , G11C2029/5002 , G11C2211/4061 , G11C2211/4067
摘要： A semiconductor memory and a refresh cycle control method that reduce a standby current by properly changing a refresh cycle according to the temperature of the semiconductor memory. A temperature detection section detects the temperature of the semiconductor memory. A cycle change control section sends a cycle change signal for changing a refresh cycle when the temperature of the semiconductor memory reaches a predetermined cycle change temperature. A refresh timing signal generation section generates a refresh timing signal and changes the cycle of the refresh timing signal in response to the cycle change signal. A constant current generation circuit generates an electric current for generating the refresh timing signal. A low-temperature constant current setting circuit designates the level of the electric current generated in the case that the temperature of the semiconductor memory is lower than or equal to the cycle change temperature. A high-temperature constant current setting circuit designates the level of the electric current generated in the case that the temperature of the semiconductor memory is higher than the cycle change temperature.
摘要翻译：一种半导体存储器和刷新周期控制方法，通过根据半导体存储器的温度适当地改变刷新周期来减少待机电流。温度检测部检测半导体存储器的温度。当半导体存储器的温度达到预定的周期变化温度时，循环变化控制部分发送用于改变刷新周期的循环改变信号。刷新定时信号生成部生成刷新定时信号，根据周期变更信号改变刷新定时信号的周期。恒流产生电路产生用于产生刷新定时信号的电流。低温恒流设定电路表示在半导体存储器的温度低于或等于循环变化温度的情况下产生的电流的电平。高温恒流设定电路表示在半导体存储器的温度高于循环变化温度的情况下产生的电流的电平。

64. 发明授权

US07394709B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07394709B2
公开(公告)日：2008-07-01
申请号：US11024734
申请日：2004-12-30
申请人： Kaoru Mori , Shinya Fujioka
发明人： Kaoru Mori , Shinya Fujioka
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C5/147 , G11C11/4094 , G11C29/02 , G11C29/025 , G11C29/12005 , G11C2029/5006 , G11C2211/4065 , G11C2211/4067
摘要： A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status.
摘要翻译：提供了一种存储器件，其具有：用于存储数据的存储器单元; 一个字线选择存储单元; 可选择的存储单元的位线; 预充电电源，用于向位线提供预充电电压; 预充电电路，用于将预充电电源连接到或从所述位线断开; 以及电流限制元件，用于根据操作状态至少两步地控制在预充电电源和位线之间流动的电流的大小。

65. 发明授权

US07379370B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07379370B2
公开(公告)日：2008-05-27
申请号：US11641767
申请日：2006-12-20
申请人： Kaoru Mori
发明人： Kaoru Mori
IPC分类号： G11C7/00
CPC分类号： G11C11/40618 , G11C11/406 , G11C11/4087
摘要： After a refresh operation, a word control circuit holds the selection state of a word line selection signal line selected in each memory block corresponding to a refresh address. Further, in response to an access request, the word control circuit unselects only a word line selection signal line of a memory block selected by an external address corresponding to this access request. In each memory block, the word line selection signal line once selected is not unselected until the access request is received, so that the frequency of unselection and selection of the word line selection signal lines can be lowered. Consequently, a charge/discharge current of the word line selection signal lines can be reduced, which can reduce current consumption of a semiconductor memory.
摘要翻译：在刷新操作之后，字控制电路保持在对应于刷新地址的每个存储块中选择的字线选择信号线的选择状态。此外，响应于访问请求，字控制电路仅取消由与该访问请求对应的外部地址选择的存储块的字线选择信号线。在每个存储器块中，一旦选择的字线选择信号线在接收到访问请求之前不被选择，从而可以降低选择和选择字线选择信号线的频率。因此，可以减小字线选择信号线的充电/放电电流，这可以减少半导体存储器的电流消耗。

66. 发明授权

US07286434B2 Semiconductor memory device with shift register-based refresh address generation circuit 有权
标题翻译：具有基于移位寄存器的刷新地址产生电路的半导体存储器件
公开(公告)号：US07286434B2
公开(公告)日：2007-10-23
申请号：US11486002
申请日：2006-07-14
申请人： Kaoru Mori , Katuhiro Mori , Shinichi Yamada , Kuninori Kawabata , Shigemasa Ito
发明人： Kaoru Mori , Katuhiro Mori , Shinichi Yamada , Kuninori Kawabata , Shigemasa Ito
IPC分类号： G11C7/00
CPC分类号： G11C11/406
摘要： A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.
摘要翻译：一种在移位寄存器的驱动控制信号中具有低功耗的半导体存储器件。该装置包含多个存储单元阵列，每个存储单元阵列由预定数量的存储单元行组成。一组移位寄存器耦合到每个单元阵列，并且第n组移位寄存器根据给定的控制信号依次激活字线选择信号，使得第n个单元阵列的相应字线将被刷新。还耦合到每个单元阵列是移位寄存器控制器。当第n个单元阵列被刷新时，第n个移位寄存器控制器向第n组移位寄存器提供控制信号。当完成该单元阵列的刷新时，第n移位寄存器控制器将控制信号转发到第（n + 1）个移位寄存器组，从而启动第（n + 1）个单元阵列的刷新操作。

67. 发明授权

US07196951B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07196951B2
公开(公告)日：2007-03-27
申请号：US11258936
申请日：2005-10-27
申请人： Kaoru Mori , Yoshiaki Okuyama
发明人： Kaoru Mori , Yoshiaki Okuyama
IPC分类号： G11C7/00
CPC分类号： G11C29/808 , G11C29/838
摘要： In order to give all memory blocks the same structure, a redundancy word line and a redundancy bit line are formed in each memory block. A redundancy column selection line is wired in common to the memory blocks. Column redundancy circuits are formed to correspond to respective memory groups each of which consists of a prescribed number of memory blocks, and become effective according to enable signals. A column redundancy selection circuit activates an enable signal according to a block address signal when all row hit signals are deactivated. When one of the row hit signals is activated, the column redundancy selection circuit activates the enable signal corresponding to the activated row hit signal. Since the column redundancy circuit for an arbitrary memory group can be made effective according to the row hit signals, failure relief efficiency can be increased without deteriorating the electric characteristic during an access operation.
摘要翻译：为了给予所有存储块相同的结构，在每个存储块中形成冗余字线和冗余位线。冗余列选择线公共地连接到存储器块。列冗余电路形成为对应于各自的存储器组，每个存储器组由规定数量的存储块组成，并且根据使能信号变为有效。当所有行命中信号被去激活时，列冗余选择电路根据块地址信号激活使能信号。当行命中信号之一被激活时，列冗余选择电路激活对应于激活的行命中信号的使能信号。由于可以根据行命中信号使任意存储器组的列冗余电路有效，可以在不使访问操作期间的电特性恶化的情况下增加故障排除效率。

68. 发明申请

US20070002648A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20070002648A1
公开(公告)日：2007-01-04
申请号：US11260200
申请日：2005-10-28
申请人： Hitoshi Ikeda , Kaoru Mori , Yoshiaki Okuyama
发明人： Hitoshi Ikeda , Kaoru Mori , Yoshiaki Okuyama
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C11/401 , G11C29/025
摘要： An equalizing circuit connects a pair of bit lines to each other in response to the activation of an equalizing control signal and connects the pair of bit lines to a precharge voltage line. An equalizing control circuit deactivates the equalizing control signal in response to the activation of a first timing signal. A word line driving circuit activates one of word lines in response to the activation of a second timing signal. A first signal generating circuit of a timing control circuit generates the first timing signal. A second signal generating circuit of the timing control circuit activates the second timing signal after the deactivation of the equalizing control signal accompanying the activation of the first timing signal. A delay control circuit of the second signal generating circuit delays an activation timing of the second timing signal in a test mode from that in a normal mode.
摘要翻译：均衡电路响应于均衡控制信号的激活而将一对位线彼此连接，并将一对位线连接到预充电电压线。均衡控制电路响应于第一定时信号的激活而去激活均衡控制信号。字线驱动电路响应于第二定时信号的激活而激活字线之一。定时控制电路的第一信号发生电路产生第一定时信号。定时控制电路的第二信号发生电路在伴随第一定时信号的激活的均衡控制信号的去激活之后激活第二定时信号。第二信号发生电路的延迟控制电路将测试模式中的第二定时信号的激活定时与正常模式中的激活定时相比较。

69. 发明申请

US20070002647A1 Semiconductor memory 有权
公开(公告)号：US20070002647A1
公开(公告)日：2007-01-04
申请号：US11258936
申请日：2005-10-27
申请人： Kaoru Mori , Yoshiaki Okuyama
发明人： Kaoru Mori , Yoshiaki Okuyama
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/838
摘要： In order to give all memory blocks the same structure, a redundancy word line and a redundancy bit line are formed in each memory block. A redundancy column selection line is wired in common to the memory blocks. Column redundancy circuits are formed to correspond to respective memory groups each of which consists of a prescribed number of memory blocks, and become effective according to enable signals. A column redundancy selection circuit activates an enable signal according to a block address signal when all row hit signals are deactivated. When one of the row hit signals is activated, the column redundancy selection circuit activates the enable signal corresponding to the activated row hit signal. Since the column redundancy circuit for an arbitrary memory group can be made effective according to the row hit signals, failure relief efficiency can be increased without deteriorating the electric characteristic during an access operation.

70. 发明授权

US07099208B2 Semiconductor memory automatically carrying out refresh operation 有权
标题翻译：半导体存储器自动执行刷新操作
公开(公告)号：US07099208B2
公开(公告)日：2006-08-29
申请号：US11011114
申请日：2004-12-15
申请人： Yoshiaki Okuyama , Kaoru Mori
发明人： Yoshiaki Okuyama , Kaoru Mori
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C29/783
摘要： An arbiter judges which of an internal access request and an external access request takes higher priority, when the internal access request conflicts with the external access request. A redundancy judgement circuit judges which of a normal memory cell and a redundancy memory cell is accessed, in accordance with each of the internal access request and the external access request. When the arbiter gives higher priority to the internal access request, the redundancy judgement circuit carries out redundancy judgement for the external access request during internal access operation. To prevent the malfunction of a memory core, a hold circuit holds redundancy judged result, and prevents the redundancy judged result for the external access request from being transmitted to the memory core that carries out the internal access operation.
摘要翻译：当内部访问请求与外部访问请求冲突时，仲裁员会判断哪个内部访问请求和外部访问请求具有较高优先级。根据内部访问请求和外部访问请求中的每一个，冗余判断电路判断访问正常存储单元和冗余存储单元中的哪一个。当仲裁器给予内部访问请求更高的优先级时，冗余判断电路在内部访问操作期间对外部访问请求执行冗余判断。为了防止存储器核心的故障，保持电路保持冗余判断结果，并且防止外部访问请求的冗余判断结果被发送到执行内部访问操作的存储器核心。

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