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61. 发明授权

US4876462A Control circuit for multipurpose input terminal 失效
标题翻译：多功能输入端子控制电路
公开(公告)号：US4876462A
公开(公告)日：1989-10-24
申请号：US200103
申请日：1988-05-31
申请人： Hiroyuki Kobatake , Toshikatsu Jinbo
发明人： Hiroyuki Kobatake , Toshikatsu Jinbo
IPC分类号： H01L27/04 , H01L21/822 , H03K17/06 , H03K17/30
CPC分类号： H03K17/06 , H03K17/302
摘要： A control circuit provided in association with a multi-purpose input node is provided with an input signal detecting circuit for relaying a middle voltage level from the multipurpose input node to the internal circuit, a charge-pump circuit activated in the presence of a high voltage level for producing an extremely high voltage level, a transferring circuit coupled between the multipurpose input node and the charge-pump circuit, and a gate transistor coupled between the multipurpose input node and the output node, and the extremely high voltage level is supplied to not only the gate transistor but also the transferring circuit, so that the high voltage level is fully transferred to the charge-pump circuit, thereby allowing the gate transistor to transfer the high voltage level to the output node without any reduction in voltage level.
摘要翻译：与多用途输入节点相关联地设置的控制电路设置有用于将中间电压电平从多功能输入节点中继到内部电路的输入信号检测电路，在存在高电压的情况下激活的电荷泵电路用于产生极高电压电平的电平，耦合在多用途输入节点和电荷泵电路之间的传输电路，以及耦合在多用途输入节点和输出节点之间的栅极晶体管，并且极高电压电平被提供给只有栅极晶体管，而且传输电路，使得高电压电平完全传输到电荷泵电路，从而允许栅极晶体管将高电压电平传送到输出节点，而不会降低电压电平。

62. 发明授权

US4847808A Read only semiconductor memory having multiple bit cells 失效
标题翻译：只读具有多个位单元的半导体存储器
公开(公告)号：US4847808A
公开(公告)日：1989-07-11
申请号：US41033
申请日：1987-04-22
申请人： Hiroyuki Kobatake
发明人： Hiroyuki Kobatake
IPC分类号： H01L27/10 , G11C11/56 , G11C17/12 , H01L21/8246 , H01L27/112 , H01L29/78
CPC分类号： H01L27/112 , G11C11/5692
摘要： For precise read-out operation at an improved speed, there is disclosed a semiconductor memory device fabricated on a semiconductor substrate of a first conductivity type and including a plurality of memory cells, each memory cell comprising (a) an insulating film covering a surface portion of the semiconductor substrate, (b) a gate electrode formed on the insulating film and located over a channel forming region in the surface portion of the semiconductor substrate, a channel being produced in the channel forming region when the memory cell is selected, (c) a first impurity region having a second conductivity type opposite to the first conductivity type and formed in the surface portion of the semiconductor substrate, the first impurity region being contiguous to the channel forming region or spaced apart from the channel forming region depending upon a bit of information stored therein, and (d) a second impurity region of the second conductivity type formed in the surface portion of the semiconductor substrate, the second impurity region being contiguous to the channel forming region or spaced apart from the channel forming region depending upon a bit of information stored therein.
摘要翻译：为了以改进的速度进行精确的读出操作，公开了一种半导体存储器件，其制造在第一导电类型的半导体衬底上并且包括多个存储单元，每个存储单元包括：（a）覆盖表面部分的绝缘膜，（b）形成在所述绝缘膜上并位于所述半导体衬底的表面部分中的沟道形成区域上方的栅电极，当选择所述存储单元时，在所述沟道形成区域中产生的沟道（c ）具有与所述第一导电类型相反并且形成在所述半导体衬底的表面部分中的第二导电类型的第一杂质区域，所述第一杂质区域邻近所述沟道形成区域或者与所述沟道形成区域间隔开，取决于位存储在其中的信息，和（d）形成在其表面部分中的第二导电类型的第二杂质区所述半导体衬底，所述第二杂质区域邻近所述沟道形成区域或者与所述沟道形成区域隔开，这取决于存储在其中的信息位。

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