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61. 发明授权

US06372653B1 Method of forming dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US06372653B1
公开(公告)日：2002-04-16
申请号：US09611563
申请日：2000-07-07
申请人： Chine-Gie Lou , Su-Yuan Chang
发明人： Chine-Gie Lou , Su-Yuan Chang
IPC分类号： H01L213065
CPC分类号： H01L21/76829 , H01L21/76811 , H01L21/76813 , H01L21/7688
摘要： A method of forming a dual damascene structure. A first organic low dielectric constant dielectric layer, a heat diffusion layer and a second organic low dielectric constant dielectric layer are formed sequentially over a substrate. A first mask layer having a via opening pattern and a second mask layer having a trench pattern are formed sequentially over the second organic. The second organic low dielectric constant dielectric layer exposed by the via opening pattern is etched using the first mask layer as a hard mask layer. The heat diffusion layer exposed by the first mask layer and the via opening in the trench region are removed using the second mask layer and the second organic low dielectric constant dielectric layer as masks. Hence, the trench pattern and the via opening pattern are transferred to the first mask layer and the heat diffusion layer, respectively. The second and the first organic low dielectric constant dielectric layer are etched using the second mask layer and the heat diffusion layer as a hard mask. Ultimately, the trench and via opening of a dual damascene structure are formed.
摘要翻译：形成双镶嵌结构的方法。在衬底上依次形成第一有机低介电常数介电层，热扩散层和第二有机低介电常数介质层。在第二有机物上依次形成具有通孔开口图案的第一掩模层和具有沟槽图案的第二掩模层。使用第一掩模层作为硬掩模层来蚀刻由通孔图案曝光的第二有机低介电常数介电层。使用第二掩模层和第二有机低介电常数介电层作为掩模去除由沟槽区域中的第一掩模层和通孔开口暴露的热扩散层。因此，沟槽图案和通孔开口图案分别转移到第一掩模层和热扩散层。使用第二掩模层和热扩散层作为硬掩模蚀刻第二和第一有机低介电常数介电层。最终，形成双镶嵌结构的沟槽和通孔开口。

62. 发明授权

US06323112B1 Method of fabricating integrated circuits 有权
标题翻译：集成电路的制造方法
公开(公告)号：US06323112B1
公开(公告)日：2001-11-27
申请号：US09498329
申请日：2000-02-04
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L2176
CPC分类号： H01L29/66545 , H01L21/28123 , H01L29/6659
摘要： A method of fabricating integrated circuits. An oxide layer and a patterned dummy gate layer are formed on a substrate. The patterned dummy gate layer is used as an implantation mask in a first ion implantation step to form a source/drain in the substrate. After performing a step to reduce the width of the patterned dummy gate layer, the narrower patterned dummy gate layer is used as an implantation mask in a second ion implantation step to form a source/drain extension in the substrate. A planarized dielectric layer is formed over the substrate; after which the dummy gate layer and the underlying oxide layer are removed to form an opening inside the dielectric layer. A gate dielectric layer and a metal gate are formed inside the opening.
摘要翻译：一种制造集成电路的方法。在基板上形成氧化物层和图案化的虚拟栅极层。图案化虚拟栅极层在第一离子注入步骤中用作注入掩模，以在衬底中形成源极/漏极。在执行降低图案化虚拟栅极层的宽度的步骤之后，在第二离子注入步骤中将较窄的图案化虚拟栅极层用作注入掩模，以在衬底中形成源极/漏极延伸。平面化介电层形成在衬底上; 之后去除伪栅极层和下面的氧化物层以在电介质层内形成开口。在开口内部形成栅介质层和金属栅极。

63. 发明授权

US06277732B1 Method of planarizing inter-metal dielectric layer 有权
标题翻译：平面化金属间介电层的方法
公开(公告)号：US06277732B1
公开(公告)日：2001-08-21
申请号：US09336045
申请日：1999-06-18
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L214763
CPC分类号： H01L21/76825 , H01L21/76834 , H01L21/76835 , H01L21/76837
摘要： A method of forming a planarized inter-metal dielectric layer. The method involves completely filling the gaps of densely packed metal line regions with low dielectric constant organic dielectric layer but only partially filling the gaps of loosely packed metal line regions. A low dielectric constant inorganic dielectric layer having a high thermal conductivity is deposited over the organic dielectric layer next. The inorganic dielectric layer also fills the remaining space in the loosely packed metal line regions not yet covered by the organic dielectric layer.
摘要翻译：形成平坦化的金属间介电层的方法。该方法包括用低介电常数有机介电层完全填充密集的金属线区域的间隙，但仅部分填充松散包装的金属线区域的间隙。接下来在有机电介质层上沉积具有高导热性的低介电常数无机介电层。无机介电层还填充尚未被有机介电层覆盖的松散填充金属线区域中的剩余空间。

64. 发明授权

US06271083B1 Method of forming a dram crown capacitor 有权
标题翻译：形成电容式电容器的方法
公开(公告)号：US06271083B1
公开(公告)日：2001-08-07
申请号：US09395187
申请日：1999-09-14
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/76895 , H01L27/10852 , H01L28/55
摘要： A method of forming a DRAM capacitor comprises the following steps in the sequence set forth. First, a first silicon oxide layer is formed on a substrate, and a nitride layer is then deposited on the first silicon oxide layer. Next, uses photolithograpy and etching process to define a contact hole, and then, fills polysilicon into the contact hole. Further, the partial polysilicon in the top contact hole is removed, sequently, W-metal (selective tungsten metal) is filled into the blank part in the top contact hole. Then, a second silicon oxide layer is deposited on surfaces of the nitride layer and the W-metal (selective tungsten metal). Subsequently, etchs back the second silicon oxide layer to form a trench, thus, the W-metal (selective tungsten metal) would be exposed in the trench. Furthermore, a barrier metal layer is formed on the surface of the trench, and a first platinum layer is formed on the barrier metal layer sequently, wherein the first platinum layer and the barrier metal layer act as the bottom electrode. Further, a dielectric layer is deposited on the first platinum layer and the second silicon oxide layer using BST material. Finally, a second platinum layer is formed on the dielectric layer to act as top electrode.
摘要翻译：形成DRAM电容器的方法包括以下所述的顺序的以下步骤。首先，在基板上形成第一氧化硅层，然后在第一氧化硅层上沉积氮化物层。接下来，使用光刻和蚀刻工艺来限定接触孔，然后将多晶硅填充到接触孔中。此外，去除顶部接触孔中的部分多晶硅，随后将W金属（选择性钨金属）填充到顶部接触孔中的坯料部分中。然后，在氮化物层和W金属（选择性钨金属）的表面上沉积第二氧化硅层。随后，蚀刻回第二氧化硅层以形成沟槽，因此，W-金属（选择性钨金属）将被暴露在沟槽中。此外，在沟槽的表面上形成阻挡金属层，并且在阻挡金属层上依次形成第一铂层，其中第一铂层和阻挡金属层用作底部电极。此外，使用BST材料在第一铂层和第二氧化硅层上沉积电介质层。最后，在介电层上形成第二铂层作为顶电极。

65. 发明授权

US06265307B1 Fabrication method for a dual damascene structure 有权
标题翻译：双镶嵌结构的制作方法
公开(公告)号：US06265307B1
公开(公告)日：2001-07-24
申请号：US09606798
申请日：2000-06-29
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L214763
CPC分类号： H01L21/02118 , H01L21/02178 , H01L21/02362 , H01L21/312 , H01L21/76811 , H01L21/76813
摘要： A dual damascene manufacturing process, which is applicable to a dual damascene structure, is described. The method includes forming sequentially a first organic dielectric layer with a low dielectric constant, a thermal diffusion layer and a second organic dielectric layer with a low dielectric constant on a substrate. A first mask layer with a trench line pattern and a second mask layer with a via opening pattern are then formed on the substrate, respectively. The second organic dielectric layer with a low dielectric constant and the thermal diffusion layer are etched using the second mask layer as a hard mask layer to transfer the via opening pattern onto the thermal diffusion layer, and the second mask layer is then removed. The first and the second organic dielectric layer with a low electric constant are removed by using the first mask layer and the thermal diffusion layer as hard mask layers to form a trench line and a via opening. After that, the dual damascene structure is completed.
摘要翻译：描述了适用于双镶嵌结构的双镶嵌制造工艺。该方法包括依次形成具有低介电常数的第一有机电介质层，在基底上具有低介电常数的热扩散层和第二有机电介质层。然后分别在基板上形成具有沟槽图案的第一掩模层和具有通孔开口图案的第二掩模层。使用第二掩模层作为硬掩模层蚀刻具有低介电常数的第二有机介电层和热扩散层，以将通孔开口图案转印到热扩散层上，然后除去第二掩模层。通过使用第一掩模层和热扩散层作为硬掩模层来去除具有低电常数的第一和第二有机介电层，以形成沟槽线和通孔。之后，双镶嵌结构完成。

66. 发明授权

US06251735B1 Method of forming shallow trench isolation structure 有权
标题翻译：形成浅沟槽隔离结构的方法
公开(公告)号：US06251735B1
公开(公告)日：2001-06-26
申请号：US09448018
申请日：1999-11-23
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L21336
CPC分类号： H01L21/76224
摘要： A method of forming a shallow trench isolation (STI) structure. A dielectric layer is formed over the interior surface of a shallow trench. Spacers are formed on the sidewalls of the shallow trench such that a portion of the dielectric layer at the bottom of the shallow trench is exposed. When a silicon oxide layer is subsequently deposited into the shallow trench using ozone and tetra-ethyl-ortho-silicate as reactive gases in a chemical vapor deposition, the silicon oxide layer is deposited faster from the dielectric layer than from the spacers.
摘要翻译：形成浅沟槽隔离（STI）结构的方法。在浅沟槽的内表面上形成电介质层。隔板形成在浅沟槽的侧壁上，使得浅沟底部的电介质层的一部分露出。当在化学气相沉积中使用臭氧和四乙基原硅酸盐作为反应气体将氧化硅层随后沉积到浅沟槽中时，氧化硅层从电介质层而不是从间隔物沉积得更快。

67. 发明授权

US06236080B1 Method of manufacturing a capacitor for high density DRAMs 有权
标题翻译：制造高密度DRAM的电容器的方法
公开(公告)号：US06236080B1
公开(公告)日：2001-05-22
申请号：US09358761
申请日：1999-07-22
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L218242
CPC分类号： H01L28/86 , H01L21/32139 , H01L27/10814 , H01L28/84 , H01L28/92
摘要： A method for manufacturing an integrated circuit capacitor is provided in the present invention. First, a semiconductor substrate is etched to form a contact hole. A conducting plug is then formed into the contact hole. Next, a dielectric layer is formed on the semiconductor substrate and the conducting plug. The dielectric layer is etched by photolithography to form an opening for exposing the top surfaces of the conducting plug and a portion of the semiconductor substrate. A plurality of discrete rugged polysilicon grains are formed on the surfaces of the dielectric layer, the conducting plug and the semiconductor substrate. The dielectric layer is next etched to form a plurality of cavities on a top surface of the dielectric layer by using the plurality of discrete rugged polysilicon grains as an etching mask. A first conducting layer is formed on the surfaces of the plurality of discrete rugged polysilicon grains, the dielectric layer, the semiconductor substrate and the conducting plug, and filling into the plurality of cavities to form a plurality of vertical fins. Then, the plurality of discrete rugged polysilicon grains and the first conducting layer are etched to define a bottom electrode. The dielectric layer is removed. A capacitor dielectric film is formed on the outer surfaces of the first conducting layer, the plurality of discrete rugged polysilicon grains and the semiconductor substrate. A second conducting layer is deposited on the outer surface of the capacitor dielectric film to serve as a top electrode.
摘要翻译：在本发明中提供了集成电路电容器的制造方法。首先，蚀刻半导体衬底以形成接触孔。然后将导电塞形成在接触孔中。接下来，在半导体衬底和导电插头上形成电介质层。通过光刻蚀刻电介质层以形成用于暴露导电插塞的顶表面和半导体衬底的一部分的开口。在电介质层，导电插塞和半导体衬底的表面上形成多个离散的坚固多晶硅颗粒。接下来蚀刻电介质层，通过使用多个离散的凹凸多晶硅晶粒作为蚀刻掩模，在电介质层的顶表面上形成多个空腔。第一导电层形成在多个分立的凹凸多晶硅晶粒，电介质层，半导体衬底和导电插塞的表面上，并且填充到多个空腔中以形成多个垂直翅片。然后，蚀刻多个离散的坚固多晶硅晶粒和第一导电层以限定底部电极。去除电介质层。在第一导电层，多个离散的坚固多晶硅晶粒和半导体衬底的外表面上形成电容器电介质膜。第二导电层沉积在电容器电介质膜的外表面上，用作顶电极。

68. 发明授权

US06187661B1 Method for fabricating metal interconnect structure 有权
标题翻译：制造金属互连结构的方法
公开(公告)号：US06187661B1
公开(公告)日：2001-02-13
申请号：US09280628
申请日：1999-03-29
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/76808 , H01L2221/1036
摘要： A method for fabricating a metal interconnect structure. A first insulating layer and a second insulating layer with a low dielectric constant are formed on a substrate in sequence. An opening is formed in the second insulating layer. A compact and high density third insulating layer is formed on the second insulating layer and in the opening to protect the second insulating layer from being damaged in a subsequent process for removing a photo-resist layer. A contact window is then formed in the third insulating layer at a bottom of the opening and the first insulating layer, so that a dual damascene opening is formed. The dual damascene opening is filled with metal with low resistivity to form the metal interconnect.
摘要翻译：一种制造金属互连结构的方法。依次在基板上形成具有低介电常数的第一绝缘层和第二绝缘层。在第二绝缘层中形成开口。在第二绝缘层和开口中形成紧凑且高密度的第三绝缘层，以保护第二绝缘层在随后的去除光致抗蚀剂层的工艺中被损坏。然后在开口的底部和第一绝缘层的第三绝缘层中形成接触窗，从而形成双镶嵌开口。双镶嵌开口填充有低电阻率的金属，形成金属互连。

69. 发明授权

US06171928B2 Method of fabricating shallow trench insolation 有权
标题翻译：制造浅沟槽日照的方法
公开(公告)号：US06171928B2
公开(公告)日：2001-01-09
申请号：US09395428
申请日：1999-09-14
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of fabricating a shallow trench isolation (STI). The method forms a spin-on glass layer after removing a pad oxide layer in a STI process in order to fill a cavity formed in an oxide layer in the vicinity of an interface between a STI and a substrate. Then, a planarization process is performed, and the spin-on glass layer is annealed into an oxide layer with good thermal stability.
摘要翻译：制造浅沟槽隔离（STI）的方法。在STI工艺中去除衬垫氧化物层之后，该方法形成旋涂玻璃层，以便填充形成在STI和衬底之间的界面附近的氧化物层中的空腔。然后，进行平面化处理，将旋涂玻璃层退火成具有良好热稳定性的氧化物层。

70. 发明授权

US6146968A Method for forming a crown capacitor 有权
标题翻译：形成冠电容器的方法
公开(公告)号：US6146968A
公开(公告)日：2000-11-14
申请号：US209047
申请日：1998-12-09
申请人： Yii-Chian Lu , Chine-Gie Lou , Shin-Puu Jeng
发明人： Yii-Chian Lu , Chine-Gie Lou , Shin-Puu Jeng
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L28/84 , H01L27/10852
摘要： A method for forming a bottom storage node of a capacitor for a DRAM memory cell on a substrate is disclosed. The method comprises the steps of: forming a first oxide layer onto the substrate; forming a conductive contact plug in the first oxide layer, the contact plug extending down to the substrate; forming a second oxide layer over the first oxide layer and the contact plug; forming a silicon nitride layer over the second oxide layer; patterning and etching the silicon nitride layer and the second oxide layer to form a trench over the contact plug; forming a layer of rugged insitu doped polysilicon layer over the silicon nitride layer and along the walls and bottom of the trench; depositing a photoresist layer over the rugged insitu doped polysilicon layer and filling the trench; performing a first reactive ion etching step until the rugged insitu doped polysilicon layer lying on the silicon nitride layer is reached; performing a second reactive ion etching step until the rugged insitu doped polysilicon layer lying on the silicon nitride layer is removed, the second reactive ion etching step formulated to remove the rugged insitu doped polysilicon layer faster than the photoresist layer; and performing a chemical dry etching step to smooth out the sharp corners of the rugged polysilicon layer.
摘要翻译：公开了一种在衬底上形成用于DRAM存储单元的电容器的底部存储节点的方法。该方法包括以下步骤：在衬底上形成第一氧化物层; 在所述第一氧化物层中形成导电接触插塞，所述接触插头向下延伸到所述衬底; 在所述第一氧化物层和所述接触插塞上形成第二氧化物层; 在所述第二氧化物层上形成氮化硅层; 图案化和蚀刻氮化硅层和第二氧化物层以在接触插塞上形成沟槽; 在氮化硅层上并且沿着沟槽的壁和底部形成一层坚固的本征掺杂多晶硅层; 在坚固的本征掺杂多晶硅层上沉积光致抗蚀剂层并填充沟槽; 执行第一反应离子蚀刻步骤，直到达到位于氮化硅层上的坚固的本征掺杂多晶硅层; 执行第二反应离子蚀刻步骤，直到去除位于氮化硅层上的坚固的本征掺杂多晶硅层，配制第二反应离子蚀刻步骤以比光致抗蚀剂层更快地去除坚固的本征掺杂多晶硅层; 并执行化学干蚀刻步骤，以平滑凹凸多晶硅层的尖角。

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