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61. 发明申请

US20090222707A1 Semiconductor memory device having capability of stable initial operation 有权
标题翻译：半导体存储器件具有稳定的初始操作能力
公开(公告)号：US20090222707A1
公开(公告)日：2009-09-03
申请号：US12217064
申请日：2008-06-30
申请人： Beom-Ju Shin , Sang-Sic Yoon
发明人： Beom-Ju Shin , Sang-Sic Yoon
IPC分类号： H03M13/09 , G06F11/10 , G06F1/12
CPC分类号： G06F11/1004
摘要： A semiconductor memory device is capable of outputting a preset logic level through an EDC pin according to an operation mode during an initial operation, and providing a stable operation according to the specification of the semiconductor memory device just after the input of a data clock (WCK). The semiconductor memory device includes an output circuit configured to output a synchronous data in response to a data clock when the data clock is enabled, and output an asynchronous data when the data clock is disabled, and a data clock detection circuit configured to control outputting the asynchronous data by checking whether the data clock is in a stable state or not.
摘要翻译：半导体存储器件能够根据初始操作期间的操作模式通过EDC引脚输出预设的逻辑电平，并且在输入数据时钟之后根据半导体存储器件的规格提供稳定的操作（WCK ）。半导体存储器件包括：输出电路，被配置为当数据时钟被使能时，响应于数据时钟输出同步数据，并且当禁止数据时钟时输出异步数据;以及数据时钟检测电路，被配置为控制输出检查异步数据是否处于稳定状态。

62. 发明授权

US07411842B2 Data arrangement control signal generator for use in semiconductor memory device 失效
标题翻译：用于半导体存储器件的数据排列控制信号发生器
公开(公告)号：US07411842B2
公开(公告)日：2008-08-12
申请号：US11024458
申请日：2004-12-30
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： G11C7/00
CPC分类号： G11C7/1018 , G11C7/1039
摘要： A data arrangement control signal generation circuit for use in a semiconductor memory device includes a plurality of data arrangement control signal generation units connected in series, each for selectively generating a data arrangement control signal according to a column address strobe (CAS) latency.
摘要翻译：用于半导体存储器件的数据排列控制信号产生电路包括串联连接的多个数据排列控制信号生成单元，每个用于根据列地址选通（CAS）等待时间选择性地产生数据排列控制信号。

63. 发明申请

US20080164919A1 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20080164919A1
公开(公告)日：2008-07-10
申请号：US11819809
申请日：2007-06-29
申请人： Jee-Yul Kim , Beom-Ju Shin
发明人： Jee-Yul Kim , Beom-Ju Shin
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/222 , G11C11/4076 , H03L7/0805 , H03L7/0812
摘要： A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock; an output control unit for generating a select signal based on a column address strobe (CAS) latency signal and a delay time corresponding to a total delay time of the DLL being in a delay locked state; and an output enable signal generating unit for generating a plurality of output enable signals in response to the DLL clock and outputting a final output enable signal in response to the select signal.
摘要翻译：半导体存储器件包括：延迟锁定环（DLL），用于延迟外部时钟以产生DLL时钟; 输出控制单元，用于基于列地址选通（CAS）延迟信号和对应于处于延迟锁定状态的DLL的总延迟时间的延迟时间来产生选择信号; 以及输出使能信号生成单元，用于响应于所述DLL时钟产生多个输出使能信号，并响应于所述选择信号输出最终的输出使能信号。

64. 发明授权

US07391671B2 Data input device for use in semiconductor memory device 有权
标题翻译：用于半导体存储器件的数据输入装置
公开(公告)号：US07391671B2
公开(公告)日：2008-06-24
申请号：US11477483
申请日：2006-06-30
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C7/1012 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： A data input device for use in a semiconductor memory device includes a synchronization control unit for receiving a data strobe signal with which a data is synchronized in order to generate a synchronization signal in response to a driving signal; and a synchronization unit for storing internal data input sequentially one-bit by one-bit into a plurality of synchronous storing elements and asynchronous storing elements and for outputting the stored data as parallel-typed aligned data all at once in synchronization with the synchronization signal.
摘要翻译：一种用于半导体存储器件的数据输入装置包括一个同步控制单元，用于接收数据同步的数据选通信号，以响应驱动信号产生同步信号; 以及同步单元，用于将内部数据以1比特比特顺序输入到多个同步存储元件和异步存储元件中，并且用于与所述同步信号同步地同时输出所存储的数据作为并行类型的对准数据。

65. 发明申请

US20080137445A1 Apparatus and method of generating DBI signal in semiconductor integrated circuit 有权
标题翻译：在半导体集成电路中产生DBI信号的装置和方法
公开(公告)号：US20080137445A1
公开(公告)日：2008-06-12
申请号：US11826765
申请日：2007-07-18
申请人： Beom Ju Shin
发明人： Beom Ju Shin
IPC分类号： G11C7/06 , G06F13/00
CPC分类号： G11C7/1006 , G11C7/1048 , G11C7/1051 , G11C7/1063
摘要： An apparatus for generating a DBI signal in a semiconductor integrated circuit includes a full adder that includes data input terminals and a carry terminal, each of which receives data, performs an operation on the received data, and outputs a sum and a carry. A DBI determining unit determines a logic value of each of the data on the basis of the sum and the carry that are transmitted from the full adder, and generates a DBI signal.
摘要翻译：一种用于在半导体集成电路中产生DBI信号的装置包括一个全加器，它包括数据输入端和一个进位端，每个进位端接收数据，对接收到的数据执行一个操作，并输出一个和和一个进位。 DBI确定单元基于从全加器发送的和和进位来确定每个数据的逻辑值，并生成DBI信号。

66. 发明授权

US07248512B2 Semiconductor memory device having controller with improved current consumption 有权
标题翻译：具有具有改善的电流消耗的控制器的半导体存储器件
公开(公告)号：US07248512B2
公开(公告)日：2007-07-24
申请号：US11157834
申请日：2005-06-22
申请人： Beom Ju Shin
发明人： Beom Ju Shin
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/4076 , G11C11/408
摘要： A semiconductor memory device wherein, in order to control the current consumed in a column address counter and latch block in a read operation, delay units disposed in the column address counter and latch block perform a shifting operation according to a signal CASP6, which is enabled in the write and read operations, and a signal WT6RD5Z, which is enabled in the write operation and disabled in the read operation. Accordingly, unnecessary current consumed in the read operation can be reduced.
摘要翻译：一种半导体存储器件，其中为了控制读取操作中的列地址计数器和锁存块中消耗的电流，设置在列地址计数器和锁存块中的延迟单元根据启用的信号CASP6执行移位操作在写入和读取操作中，以及信号WT6RD5Z，其在写入操作中被使能并且在读取操作中被禁用。因此，可以减少在读取操作中消耗的不必要的电流。

67. 发明申请

US20070071074A1 Data input device for use in semiconductor memory device 有权
标题翻译：用于半导体存储器件的数据输入装置
公开(公告)号：US20070071074A1
公开(公告)日：2007-03-29
申请号：US11477483
申请日：2006-06-30
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： H04B1/00
CPC分类号： G11C7/1039 , G11C7/1012 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： A data input device for use in a semiconductor memory device includes a synchronization control unit for receiving a data strobe signal with which a data is synchronized in order to generate a synchronization signal in response to a driving signal; and a synchronization unit for storing internal data input sequentially one-bit by one-bit into a plurality of synchronous storing elements and asynchronous storing elements and for outputting the stored data as parallel-typed aligned data all at once in synchronization with the synchronization signal.
摘要翻译：一种用于半导体存储器件的数据输入装置包括一个同步控制单元，用于接收数据同步的数据选通信号，以响应驱动信号产生同步信号; 以及同步单元，用于将内部数据以1比特比特顺序输入到多个同步存储元件和异步存储元件中，并且用于与所述同步信号同步地同时输出所存储的数据作为并行类型的对准数据。

68. 发明申请

US20070070712A1 Data input/output multiplexer of semiconductor device 有权
标题翻译：半导体器件的数据输入/输出多路复用器
公开(公告)号：US20070070712A1
公开(公告)日：2007-03-29
申请号：US11529286
申请日：2006-09-29
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096
摘要： There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line.
摘要翻译：提供了一种输入/输出多路复用器，其能够通过在特定数据输入/输出（I / O）板的任一侧布置第一和第二多路复用器来减少设计设备中的布局面积。用于复用输入或输出到全局输入/输出（I / O）线路的数据的装置包括：第一多路复用器，用于复用数据并将第一多路复用数据提供给全局I / O线;以及第二多路复用器，提供给全局I / O线的数据，其中第一和第二多路复用器形成在全局I / O线的任一侧。

69. 发明授权

US07006402B2 Multi-port memory device 失效
标题翻译：多端口存储设备
公开(公告)号：US07006402B2
公开(公告)日：2006-02-28
申请号：US10750156
申请日：2003-12-31
申请人： Byung-Il Park , Beom-Ju Shin
发明人： Byung-Il Park , Beom-Ju Shin
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C7/1048
摘要： A multi-port memory device includes a plurality of banks arranged at an upper and a lower portion of a core area as many as a fixed number in a row direction, a multiplicity of ports located at edges of the upper and the lower portions of the core area, wherein respective ports perform independent communication with respective different target devices, a first global data bus, located in a row direction between the ports and the banks arranged at the upper portion of the core area, for performing the parallel data transmission, a second global data bus, located in a row direction between the ports and the banks arranged at the lower portion of the core area, for performing the parallel data transmission, many local data buses, arranged in a column direction of each bank, for executing data transmission within the banks, and a majority of local data bus connection units, located between two banks adjacent to each other in a column direction, for selectively connecting the local data buses corresponding to the two adjacent banks.
摘要翻译：多端口存储器件包括布置在排列在行方向上固定数量的核心区域的上部和下部的多个存储体，位于所述多个端口的上部和下部的边缘处的多个端口核心区域，其中相应的端口与各个不同的目标设备执行独立的通信，第一全局数据总线位于布置在核心区域的上部的端口和存储体之间的行方向上，用于执行并行数据传输，第二全局数据总线，位于布置在核心区域的下部的端口和存储体之间的行方向上，用于执行并行数据传输，许多局部数据总线布置在每个存储体的列方向上，用于执行数据并且在列方向上彼此相邻的两个组之间的大多数本地数据总线连接单元，用于选择性地连接本地数据总线对应于两个相邻的银行。

70. 发明申请

US20050249019A1 Bus connection circuit for read operation of multi-port memory device 有权
标题翻译：总线连接电路，用于多端口存储器件的读取操作
公开(公告)号：US20050249019A1
公开(公告)日：2005-11-10
申请号：US10876504
申请日：2004-06-24
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： G11C5/06 , G11C7/06 , G11C7/10 , G11C8/16 , G11C11/4091 , G11C11/4096
CPC分类号： G11C5/063 , G11C7/065 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1075 , G11C8/16 , G11C11/4091 , G11C11/4096 , G11C2207/002
摘要： There is provided a semiconductor memory design technique, specifically a bus connection circuit for a read operation of a multi-port memory device. The bus connection circuit is adapted to a current sensing type bus transmission/reception structure. The bus connection circuit includes: a read data sensing/latching unit for sensing/latching a read data applied on a local data bus in response to a read data strobe signal; and a read data driving unit for driving the data latched in the read data sensing/latching unit to a global data bus in response to a read data driving pulse, and for connecting or disconnecting a path of current flowing the global data bus according to a logic level of the latched data.
摘要翻译：提供了半导体存储器设计技术，特别是用于多端口存储器件的读取操作的总线连接电路。总线连接电路适用于电流感测型总线发送/接收结构。总线连接电路包括：读取数据感测/锁存单元，用于响应于读取的数据选通信号来感测/锁存施加在本地数据总线上的读取数据; 以及读取数据驱动单元，用于响应于读取的数据驱动脉冲将锁存在读取数据感测/锁存单元中的数据驱动到全局数据总线，并且根据读取数据驱动脉冲连接或断开流动全局数据总线的电流的路径锁存数据的逻辑电平。

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