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    • 61. 发明授权
    • Method and structures of monolithically integrated ESD suppression device
    • 单片集成ESD抑制器的方法和结构
    • US08148781B2
    • 2012-04-03
    • US12511002
    • 2009-07-28
    • Xiao (Charles) Yang
    • Xiao (Charles) Yang
    • H01L27/12H01L31/0392
    • H01L27/0248H01L23/60H01L24/05H01L2924/14H01L2924/00
    • This present invention relates in general to protection of integrated circuit chips, and more particularly, to a micromachined suppression device for protecting integrated circuit chips from electrostatic discharges. The proposed ESD suppression device consists of conductive pillars are dispersed in a dielectric material. The gaps between each pillar behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed ESD suppression device is fabricated using micromachining techniques to be on-chip with device ICs.
    • 本发明一般涉及集成电路芯片的保护,更具体地,涉及用于保护集成电路芯片免受静电放电的微加工抑制装置。 所提出的ESD抑制装置由导电柱分散在电介质材料中。 当发生高电压ESD脉冲时,每个支柱之间的间隙就像火花隙。 当脉冲电压达到“触发电压”时,这些间隙发生火花,产生非常低的电阻路径。 在正常工作中,由于导电柱之间的物理间隙,漏电流和电容非常低。 所提出的ESD抑制装置是使用微加工技术制造的,与芯片集成在一起。
    • 70. 发明授权
    • Method and structure of MEMS WLCSP fabrication
    • MEMS WLCSP制作的方法和结构
    • US09540232B2
    • 2017-01-10
    • US14507177
    • 2014-10-06
    • mCube Inc.
    • Chien Chen Lee
    • B81C1/00
    • B81C1/00301B81B2201/0235B81B2201/0242B81B2201/0257B81B2201/0264B81C2203/0109B81C2203/0154
    • A method for fabricating a MEMS-IC device structure can include receiving a CMOS substrate comprising a plurality of CMOS circuits and a surface portion. A MEMS substrate having at least one MEMS device can be received and coupled to the CMOS substrate. The MEMS substrate and the surface portion of the CMOS substrate can be encapsulated with a molding material, which forms a top surface. A first plurality of vias can be created in the molding material from the top surface to the surface portion of the CMOS substrate. A conductive material can be disposed within the first plurality of vias such that the conductive material is electrically coupled to a portion of the CMOS substrate. A plurality of interconnects can be formed from the conductive material to the top surface of the molding material and a plurality of solder balls can be formed upon these interconnects.
    • 制造MEMS-IC器件结构的方法可以包括接收包括多个CMOS电路和表面部分的CMOS衬底。 具有至少一个MEMS器件的MEMS衬底可被接收并耦合到CMOS衬底。 MEMS衬底和CMOS衬底的表面部分可以用形成顶表面的成型材料封装。 可以在模制材料中从CMOS衬底的顶表面到表面部分形成第一多个通孔。 导电材料可以设置在第一多个通孔内,使得导电材料电耦合到CMOS衬底的一部分。 可以从导电材料形成多个互连件到模制材料的顶表面,并且可以在这些互连件上形成多个焊球。