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51. 发明授权

US06492197B1 Trilayer/bilayer solder bumps and fabrication methods therefor 有权
标题翻译：三层/双层焊料凸块及其制造方法
公开(公告)号：US06492197B1
公开(公告)日：2002-12-10
申请号：US09576477
申请日：2000-05-23
申请人： Glenn A. Rinne
发明人： Glenn A. Rinne
IPC分类号： H01L2144
CPC分类号： H01L24/12 , H01L21/4853 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/11462 , H01L2224/1147 , H01L2224/11472 , H01L2224/11502 , H01L2224/11849 , H01L2224/11901 , H01L2224/13017 , H01L2224/1308 , H01L2224/131 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H05K3/3463 , H05K3/3473 , H05K2201/10992 , H01L2224/13099 , H01L2924/00
摘要： Solder bumps are fabricated by plating a first solder layer on an underbump metallurgy, plating a second solder layer having higher melting point than the first solder layer on the first solder layer and plating a third solder layer having lower melting point than the second solder layer on the second solder layer. The structure then is heated to below the melting point of the second solder layer but above the melting point of the first solder layer and the third solder layer, to alloy at least some of the first solder layer with at least some of the underbump metallurgy and to round the third solder layer. Accordingly, a trilayer solder bump may be fabricated wherein the first and third layers melt at lower temperatures than the second solder layer, to thereby round the outer surface of the solder bump and alloy the base of the solder bump to the underbump metallurgy, while allowing the structure of the intermediate layer to be preserved. Solder bump fabrication as described above may be particularly useful with lead-tin solder wherein the first solder layer is eutectic lead-tin solder, the second solder layer is lead-tin solder having higher lead content than eutectic lead-tin solder and the third solder layer is eutectic lead-tin solder. In yet other embodiments, the thickness and/or composition of the outer underbump metallurgy layer and/or of the first solder layer may be selected so that upon heating, sufficient tin from the first solder layer is alloyed with at least some of the outer underbump metallurgy layer, such that the first solder layer is converted to a fourth solder layer having the same lead content as the second solder layer. Bilayer solder bumps thereby may be provided.
摘要翻译：通过在下焊管冶金上电镀第一焊料层，在第一焊料层上电镀具有比第一焊料层更高的熔点的第二焊料层并且将具有比第二焊料层低的熔点的第三焊料层电镀到第二焊料层上来制造焊料凸块第二焊料层。然后将该结构加热到低于第二焊料层的熔点但高于第一焊料层和第三焊料层的熔点，以使第一焊料层中的至少一些与至少一些下焊管冶金和绕第三个焊料层。因此，可以制造三层焊料凸块，其中第一和第三层在比第二焊料层更低的温度下熔化，从而使焊料凸块的外表面圆周化，并将焊料凸块的底部合金到底部焊接冶金，同时允许待保存的中间层的结构。如上所述的焊料凸块制造对于铅锡焊料尤其有用，其中第一焊料层是共晶铅锡焊料，第二焊料层是比共晶铅锡焊料具有更高铅含量的铅锡焊料，而第三焊料层是共晶铅锡焊料。在另外的其它实施例中，可以选择外部底部基质金属层和/或第一焊料层的厚度和/或组成，使得在加热时，来自第一焊料层的足够的锡与至少一些外部底部基底使得第一焊料层被转换成具有与第二焊料层相同的铅含量的第四焊料层。可以提供双层焊料凸块。

52. 发明申请

US20020173135A1 Bump transfer plate, manufacturing method thereof, semiconductor device, and manufacturing method thereof 审中-公开
公开(公告)号：US20020173135A1
公开(公告)日：2002-11-21
申请号：US10191141
申请日：2002-07-09
申请人： NEC Corporation
发明人： Hiroyuki Tsukui , Chikara Yamashita , Tetsuya Tao
IPC分类号： H01L021/44
CPC分类号： H01L24/11 , H01L21/4853 , H01L2224/05573 , H01L2224/11003 , H01L2224/11334 , H01L2224/1147 , H01L2224/13099 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H05K3/3473 , H05K2203/0152 , H05K2203/0338 , H05K2203/0726 , H01L2224/05599
摘要： A bump formation plate is provided with a base and solder bumps formed on the base. The top portion of the solder bump inclines from the center thereof to the periphery thereof. A contact surface of the solder bump with the base may be flat. The base is made of, for example, aluminum or stainless steel.

53. 发明授权

US06387793B1 Method for manufacturing precision electroplated solder bumps 失效
标题翻译：精密电镀焊料凸块的制造方法
公开(公告)号：US06387793B1
公开(公告)日：2002-05-14
申请号：US09522803
申请日：2000-03-09
申请人： Daniel Yap , Phillip H. Lawyer
发明人： Daniel Yap , Phillip H. Lawyer
IPC分类号： H01L2144
CPC分类号： H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05567 , H01L2224/05568 , H01L2224/10126 , H01L2224/13007 , H01L2224/131 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/1423 , H01L2924/19042 , H05K3/3473 , H01L2224/13099 , H01L2224/29099 , H01L2224/05552
摘要： A method for fabrication of a solder bump, comprising applying preferably an insulating film, followed by applying a multilayer underbump metallization, a layer of a photoresist, and a thin layer of titanium on a substrate containing, preferably, III-V semiconductor circuits. The multilayer UBM pad, preferably comprising a 0.02 to 0.05 micrometer thick layer of titanium, a 0.5 to 1.0 micrometer thick layer of nickel and a 0.1 to 0.2 thick layer of gold. The protective film with the thickness of preferably 0.5 to 40 micrometer comprises a photoresist. After the solder has been electroplated, the protective film is removed, preferably by dry etching or with a solvent. The titanium film serves a dual function of being a membrane for electroplating of the solder and of being a non-wettable dam for wetting back of the plated solder. The titanium film with the thickness of 200 to 1,000 Angstroms is preferably deposited by evaporation. After the solder has been electroplated, much of the titanium film is removed, preferably by wet etching or dry etching, leaving only a band of titanium that surrounds the disk of solder. A multilayer solder bump structure for III-V semiconductor circuits manufactured using this method, comprising, preferably, an insulating film, a multilayer underbump metallization layer, and remnants of the thin titanium film.
摘要翻译：一种用于制造焊料凸块的方法，包括优选地施加绝缘膜，然后在包含优选III-V半导体电路的基板上施加多层下凹凸金属化，光致抗蚀剂层和钛薄层。多层UBM垫，优选包含0.02至0.05微米厚的钛层，0.5至1.0微米厚的镍层和0.1至0.2厚度的金层。厚度优选为0.5至40微米的保护膜包括光致抗蚀剂。在焊料被电镀之后，优选通过干蚀刻或溶剂去除保护膜。钛膜具有双重功能，即作为用于电镀焊料的膜和作为用于润湿镀覆焊料的不可润湿的坝的双重功能。优选通过蒸发沉积厚度为200至1000埃的钛膜。在焊料被电镀之后，大部分钛膜被去除，优选通过湿蚀刻或干蚀刻，仅留下围绕焊料盘的钛带。使用该方法制造的III-V半导体电路的多层焊料凸块结构，优选包括绝缘膜，多层下凸块金属化层和薄钛膜的残余物。

54. 发明授权

US06348401B1 Method of fabricating solder bumps with high coplanarity for flip-chip application 有权
标题翻译：制造用于倒装芯片应用的具有高共面性的焊料凸块的方法
公开(公告)号：US06348401B1
公开(公告)日：2002-02-19
申请号：US09709908
申请日：2000-11-10
申请人： Chih-Shun Chen , Chao-Dung Suo , Jui-Meng Jao , Ke-Chuan Yang , Feng-Lung Chien
发明人： Chih-Shun Chen , Chao-Dung Suo , Jui-Meng Jao , Ke-Chuan Yang , Feng-Lung Chien
IPC分类号： H01L2144
CPC分类号： H01L24/05 , H01L24/02 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05572 , H01L2224/05599 , H01L2224/11462 , H01L2224/1147 , H01L2224/11502 , H01L2224/11849 , H01L2224/119 , H01L2224/11901 , H01L2224/131 , H01L2924/00013 , H01L2924/0002 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H05K3/3473 , H05K3/3484 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099 , H01L2224/05552 , H01L2224/1146
摘要： A solder-pump fabrication method is proposed, which is used for the fabrication of solder bumps with high coplanarity over a semiconductor chip for flip-chip application. The proposed solder-bump fabrication method is characterized in the use of a two-step solder-bump fabrication process, including a first step of electroplating solder over UBM (Under Bump Metallization) pads to a controlled height still below the topmost surface of the mask, and a second step of screen-printing solder paste over the electroplated solder layer. The combined structure of the electroplated solder layer and the printed solder layer is then reflowed to form the desired solder bump. Since the proposed solder-bump fabrication method allows the solder material electroplated and printed over the UBM pads to be confined within the mask openings and never exceed the topmost surface of the mask, the resulted solder bumps would not be bridged to neighboring ones. Moreover, the proposed solder-bump fabrication method allows all the resulted solder bumps to be substantially equally sized to achieve high coplanarity.
摘要翻译：提出了一种焊料泵制造方法，其用于在用于倒装芯片的半导体芯片上制造具有高共面性的焊料凸块。所提出的焊料凸点制造方法的特征在于使用两步骤焊料凸块制造工艺，其包括将UBM（低于Bump金属化）焊盘上的焊料电镀到仍然低于掩模的最上表面的受控高度的第一步骤以及在电镀焊料层上丝网印刷焊膏的第二步骤。然后将电镀焊料层和印刷焊料层的组合结构回流以形成所需的焊料凸点。由于所提出的焊料凸点制造方法允许在UBM焊盘上电镀和印刷的焊料材料被限制在掩模开口内，并且不会超过掩模的最上表面，所以产生的焊料凸点不会被桥接到相邻焊盘。此外，所提出的焊料凸块制造方法允许所有所得到的焊料凸块基本相同的尺寸以实现高共面性。

55. 发明授权

US06281693B1 Semiconductor device test board and a method of testing a semiconductor device 失效
标题翻译：半导体器件测试板和测试半导体器件的方法
公开(公告)号：US06281693B1
公开(公告)日：2001-08-28
申请号：US09088709
申请日：1998-06-02
申请人： Jun Fukuda
发明人： Jun Fukuda
IPC分类号： G01R106
CPC分类号： H05K3/3436 , G01R1/0483 , H01L24/14 , H01L24/81 , H01L2224/14515 , H01L2924/15787 , H05K3/244 , H05K3/28 , H05K3/3473 , H05K2201/10674 , H05K2203/162 , Y02P70/613 , H01L2924/00
摘要： A semiconductor device test board for performing a test on a semiconductor device includes a supporting board formed of an insulating material and contact parts which are formed on the supporting board, and which can be connected to solder bumps formed on a semiconductor device to be tested. Each of the contact parts includes contact base layers formed of conductive materials other than solder and a solder layer having a thin-film shape, and covering the contact base layers.
摘要翻译：用于对半导体器件进行测试的半导体器件测试板包括由绝缘材料形成的支撑板和形成在支撑板上的接触部分，并且可以连接到形成在待测试的半导体器件上的焊料凸块。每个接触部分包括由焊料以外的导电材料形成的接触基底层和具有薄膜形状的焊料层，并覆盖接触基底层。

56. 发明申请

US20010015495A1 Process for forming cone shaped solder for chip interconnection 失效
公开(公告)号：US20010015495A1
公开(公告)日：2001-08-23
申请号：US09753819
申请日：2001-01-03
申请人： International Business Machines Corporation
发明人： Peter J. Brofman , Shaji Farooq , John U. Knickerbocker , Scott I. Langenthal , Sudipta K. Ray , Kathleen A. Stalter
IPC分类号： H01L023/48 , H01L023/52 , H01L029/40
CPC分类号： H01L24/81 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05666 , H01L2224/05671 , H01L2224/0603 , H01L2224/06505 , H01L2224/10135 , H01L2224/11002 , H01L2224/11472 , H01L2224/1184 , H01L2224/13017 , H01L2224/13019 , H01L2224/13082 , H01L2224/13111 , H01L2224/13116 , H01L2224/14 , H01L2224/1403 , H01L2224/14051 , H01L2224/141 , H01L2224/14505 , H01L2224/16058 , H01L2224/16238 , H01L2224/81136 , H01L2224/81139 , H01L2224/8121 , H01L2224/81815 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/351 , H05K3/303 , H05K3/3436 , H05K3/3457 , H05K3/3473 , H05K2201/10992 , H05K2201/2036 , H05K2203/0113 , H05K2203/0465 , Y02P70/613 , H01L2924/00 , H01L2924/01083 , H01L2924/013 , H01L2924/00013 , H01L2924/00014
摘要： A method of forming non-spherically shaped solder interconnects, preferably conical, for attachment of electronic components in an electronic module. Preferably, the solder interconnects of the present invention are cone shaped and comprise of depositing a first solder followed by a second solder having a lower reflow temperature than the first solder. Warm placement of the electronic component at a somewhat elevated temperature than room temperature but less than the solder reflow temperature reduces the force required during placement of a semiconductor chip to a substrate. After warm placement, reflow of the module occurs at the lower reflow temperature of the second solder. The conical shape of the solder interconnects are formed by a heated coining die which may also coin a portion of the interconnects with flat surfaces for stand-offs. The ability of the cone shaped solder interconnects to meet the opposing surface of a chip or substrate at different heights accommodates the camber typically associated with chip and substrate surfaces.

57. 发明授权

US06184062B2 Process for forming cone shaped solder for chip interconnection 有权
标题翻译：用于形成用于芯片互连的锥形焊料的工艺
公开(公告)号：US06184062B2
公开(公告)日：2001-02-06
申请号：US09233383
申请日：1999-01-19
申请人： Peter Jeffrey Brofman , Shaji Farooq , John U. Knickerbocker , Scott Ira Langenthal , Sudipta Kumar Ray , Kathleen Ann Stalter
发明人： Peter Jeffrey Brofman , Shaji Farooq , John U. Knickerbocker , Scott Ira Langenthal , Sudipta Kumar Ray , Kathleen Ann Stalter
IPC分类号： H01L2144
CPC分类号： H01L24/81 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05666 , H01L2224/05671 , H01L2224/0603 , H01L2224/06505 , H01L2224/10135 , H01L2224/11002 , H01L2224/11472 , H01L2224/1184 , H01L2224/13017 , H01L2224/13019 , H01L2224/13082 , H01L2224/13111 , H01L2224/13116 , H01L2224/14 , H01L2224/1403 , H01L2224/14051 , H01L2224/141 , H01L2224/14505 , H01L2224/16058 , H01L2224/16238 , H01L2224/81136 , H01L2224/81139 , H01L2224/8121 , H01L2224/81815 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/351 , H05K3/303 , H05K3/3436 , H05K3/3457 , H05K3/3473 , H05K2201/10992 , H05K2201/2036 , H05K2203/0113 , H05K2203/0465 , Y02P70/613 , H01L2924/00 , H01L2924/01083 , H01L2924/013 , H01L2924/00013 , H01L2924/00014
摘要： A method of forming non-spherically shaped solder interconnects, preferably conical, for attachment of electronic components in an electronic module. Preferably, the solder interconnects of the present invention are cone shaped and comprise of depositing a first solder followed by a second solder having a lower reflow temperature than the first solder. Warm placement of the electronic component at a somewhat elevated temperature than room temperature but less than the solder reflow temperature reduces the force required during placement of a semiconductor chip to a substrate. After warm placement, reflow of the module occurs at the lower reflow temperature of the second solder. The conical shape of the solder interconnects are formed by a heated coining die which may also coin a portion of the interconnects with flat surfaces for stand-offs. The ability of the cone shaped solder interconnects to meet the opposing surface of a chip or substrate at different heights accommodates the camber typically associated with chip and substrate surfaces.
摘要翻译：形成用于将电子部件附接到电子模块中的非球形焊料互连（优选为圆锥形）的方法。优选地，本发明的焊料互连件是锥形的，并且包括沉积第一焊料，接着是具有比第一焊料低的回流温度的第二焊料。电子部件在比室温略高的温度但低于焊料回流温度的温度放置降低了将半导体芯片放置到衬底期间所需的力。在温热放置之后，模块的回流在第二焊料的较低回流温度下发生。焊接互连的圆锥形由加热的压印模具形成，其也可以将一部分互连件用平坦表面硬化以用于支架。锥形焊料互连件在不同高度处与芯片或基板的相对表面相遇的能力适应通常与芯片和基板表面相关联的外倾。

58. 发明授权

US6099713A Tin-silver alloy electroplating bath and tin-silver alloy electroplating process 失效
标题翻译：锡银合金电镀浴和锡 - 银合金电镀工艺
公开(公告)号：US6099713A
公开(公告)日：2000-08-08
申请号：US977658
申请日：1997-11-24
申请人： Isamu Yanada , Masanobu Tsujimoto
发明人： Isamu Yanada , Masanobu Tsujimoto
IPC分类号： C25D3/60 , H05K3/34 , C25D3/56
CPC分类号： H05K3/3473 , C25D3/60 , H05K3/3463
摘要： Disclosed is a tin-silver alloy electroplating bath containing: (A) stannous salt; (B) silver salt; (C) one kind or two or more kinds of acids selected from the group consisting of sulfuric acid, phosphoric acid, phosphonic acid, hydroxycarboxylic acid, alkanesulfonic acid, and alkanolsulfonic acid; (D) thiourea; (E) nonionic surface active agent; and (F) one kind or two or more kinds of additives selected from the group consisting of a mercapto group containing aromatic compound, dioxyaromatic compound, and unsaturated carboxylic acid. The electroplating using the above electroplating bath is allowed to form a homogeneous tin-silver alloy plated film having a good external appearance by eliminating preferential deposition of silver and substitutional deposition of silver on an anode and the plated film.
摘要翻译：公开了一种锡 - 银合金电镀浴，其含有：（A）亚锡盐; （B）银盐; （C）选自硫酸，磷酸，膦酸，羟基羧酸，链烷磺酸和烷醇磺酸中的一种或两种以上的酸; （D）硫脲; （E）非离子表面活性剂; 和（F）选自由含巯基的芳族化合物，二氧杂芳族化合物和不饱和羧酸组成的组中的一种或两种以上的添加剂。使用上述电镀浴的电镀通过消除银的优先沉积和银的替代沉积在阳极和镀膜上形成具有良好外观的均匀的锡 - 银合金镀膜。

59. 发明授权

US5895231A External terminal fabrication method for semiconductor device package 失效
标题翻译：半导体器件封装的外部端子制造方法
公开(公告)号：US5895231A
公开(公告)日：1999-04-20
申请号：US960210
申请日：1997-10-29
申请人： Jong Hae Choi , Jin Sung Kim
发明人： Jong Hae Choi , Jin Sung Kim
IPC分类号： H01L21/60 , H01L21/321 , H01L21/48 , H01L23/12 , H01L23/498 , H05K1/03 , H05K3/34 , H01L21/44 , H01L21/50
CPC分类号： H01L23/49816 , H01L21/4853 , H05K3/3473 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/15174 , H01L2924/15184 , H01L2924/181 , H05K1/0306 , H05K2203/072 , H05K2203/0769 , H05K3/3452
摘要： An external terminal fabrication method for a ball grid array (BGA) semiconductor package for directly forming a bump on a substrate includes the steps of forming a plurality of conductive islands spaced from each other on an upper surface of a substrate, forming a photoresist film on the substrate, exposing the respective islands through the photoresist film, forming a conductive bump member on each of the exposed islands, and removing the photoresist film remaining on the substrate.
摘要翻译：用于在衬底上直接形成凸块的球栅阵列（BGA）半导体封装的外部端子制造方法包括以下步骤：在衬底的上表面上形成彼此间隔开的多个导电岛，形成光致抗蚀剂膜衬底，使相应的岛暴露于光致抗蚀剂膜上，在每个暴露的岛上形成导电凸起构件，以及去除残留在衬底上的光致抗蚀剂膜。

60. 发明授权

US5863406A Method of manufacturing a printed circuit board 失效
标题翻译：印刷电路板的制造方法
公开(公告)号：US5863406A
公开(公告)日：1999-01-26
申请号：US809334
申请日：1997-05-19
申请人： Roberto Mazzoni , Adelio Monzani , Vittorio Sirtori
发明人： Roberto Mazzoni , Adelio Monzani , Vittorio Sirtori
IPC分类号： H05K3/24 , H05K3/34 , H05K3/42 , C25D5/02
CPC分类号： H05K3/3473 , H05K3/428 , H05K2203/0485 , H05K2203/0542 , H05K3/243 , H05K3/3489 , Y10T29/49144
摘要： A method of manufacturing a printed circuit board adapted for having surface mounted components positioned thereon including the step of selectively electroplating a thick solder layer (340) onto selected conductive projections (230). The selective electrodeposition is performed by electrolessly applying a conductive layer (310) onto the board (100) previously provided with circuit conductors (220) and conductive projections (230), providing a thick insulating mask (310) leaving exposed the selected conductive projections (230), and electroplating the thick solder layer (340). The method of manufacturing an electronic card by surface mounting of components (SMT) onto the printed circuit board (100) obtainable by the above-described method further includes the step of dispensing a flux, preferably a no-clean flux dispensed by syringe, onto the board (100), avoiding solder paste application or adhesive screening.
摘要翻译： PCT No.PCT / EP95 / 02634 371日期1997年5月19日 102（e）日期1997年5月19日PCT提交1995年7月6日PCT公布。出版物WO97 / 02727 日期1997年1月23日制造适于具有位于其上的表面安装部件的印刷电路板的方法包括将厚焊料层（340）选择性地电镀到选定的导电突起（230）上的步骤。通过将导电层（310）无电地施加到预先设置有电路导体（220）和导电突起（230）的板（100）上，从而提供厚的绝缘掩模（310），使所选择的导电突起 230），并且电镀厚焊料层（340）。通过将组件（SMT）表面安装到可通过上述方法获得的印刷电路板（100）上制造电子卡的方法还包括将助熔剂，优选地由注射器分配的免清洗助剂分配到板（100），避免焊膏应用或粘合剂筛选。

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