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51. 发明授权

US07634584B2 Packet validation in virtual network interface architecture 有权
标题翻译：虚拟网络接口架构中的数据包验证
公开(公告)号：US07634584B2
公开(公告)日：2009-12-15
申请号：US11116018
申请日：2005-04-27
申请人： Steve Pope , David Riddoch , Ching Yu , Derek Roberts
发明人： Steve Pope , David Riddoch , Ching Yu , Derek Roberts
IPC分类号： G06F15/16
CPC分类号： H04L63/10 , H04L47/50 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9063
摘要： Roughly described, a network interface device receiving data packets from a computing device for transmission onto a network, the data packets having a certain characteristic, transmits the packet only if the sending queue has authority to send packets having that characteristic. The data packet characteristics can include transport protocol number, source and destination port numbers, source and destination IP addresses, for example. Authorizations can be programmed into the NIC by a kernel routine upon establishment of the transmit queue, based on the privilege level of the process for which the queue is being established. In this way, a user process can use an untrusted user-level protocol stack to initiate data transmission onto the network, while the NIC protects the remainder of the system or network from certain kinds of compromise.
摘要翻译：大体上描述了一种从计算设备接收数据包以便传输到网络上的网络接口设备，具有一定特性的数据分组仅在发送队列具有发送具有该特性的分组的权限时发送分组。数据包特征可以包括传输协议号，源和目的端口号，源和目的IP地址。基于建立队列的进程的权限级别，可以通过内核例程在建立传输队列时将授权编程到NIC中。以这种方式，用户进程可以使用不受信任的用户级协议栈来发起到网络上的数据传输，而NIC保护系统或网络的其余部分免受某些种类的折中。

52. 发明申请

US20090144493A1 Circular Buffer Maping 审中-公开
标题翻译：循环缓冲区映射
公开(公告)号：US20090144493A1
公开(公告)日：2009-06-04
申请号：US11948922
申请日：2007-11-30
申请人： Vladimir Stoyanov
发明人： Vladimir Stoyanov
IPC分类号： G06F12/00
CPC分类号： H04L49/9031 , H04L49/90
摘要： Techniques for mirroring circular buffer mapping are discussed. Mirroring mapping for buffered message data, such as streaming data which may permit rapid data access for message data is circularly buffered. A first map and a second map may be linearly arranged in virtual memory space such that a reading of the first and or second maps, beginning from a fixed position within one of the maps, may permit parsing of the message data as if, the message was linearly arranged in the buffer.
摘要翻译：讨论了循环缓冲区映射的技术。用于缓冲消息数据的镜像映射，例如可能允许快速数据访问消息数据的流数据被循环缓冲。第一地图和第二地图可以线性地布置在虚拟存储器空间中，使得从地图之一内的固定位置开始的第一和/或第二地图的读取可以允许解析消息数据，好像消息在缓冲器中线性排列。

53. 发明申请

US20090109844A1 Terminal Of Portable Internet System And Method Of Transmitting Uplink Data In Terminal 有权
标题翻译：便携式互联网系统终端和终端上传数据的方法
公开(公告)号：US20090109844A1
公开(公告)日：2009-04-30
申请号：US11792222
申请日：2005-05-17
申请人： Seung-Que Lee , Nam-Hoon Park , Jee-Hwan Ahn
发明人： Seung-Que Lee , Nam-Hoon Park , Jee-Hwan Ahn
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L47/14 , H04L47/2441 , H04L47/32 , H04L47/50 , H04L49/9031
摘要： A terminal of a portable Internet system comprising a medium access control (MAC) layer and a physical layer, the MAC layer comprising: a classifier classifying packets into classes; a delayer calling queue operating functions when a predetermined period of time is passed after the packets are classified by the classifier; a wait queue storing packets by the queue operating functions; and a packet processor processing the packet in the wait queue and transmitting the processed packet to the physical layer.
摘要翻译：一种包括介质访问控制（MAC）层和物理层的便携式因特网系统的终端，所述MAC层包括：分类器将分组分类成类; 延迟器在通过分类器分类分组之后经过预定时间段时调用队列操作功能; 等待队列通过队列操作功能存储数据包; 以及分组处理器处理等待队列中的分组并将处理的分组发送到物理层。

54. 发明授权

US07468985B2 System independent and scalable packet buffer management architecture for network processors 有权
标题翻译：用于网络处理器的系统独立且可扩展的数据包缓冲管理架构
公开(公告)号：US07468985B2
公开(公告)日：2008-12-23
申请号：US10290766
申请日：2002-11-08
申请人： Faraydon O. Karim , Ramesh Chandra , Bernd H. Stramm
发明人： Faraydon O. Karim , Ramesh Chandra , Bernd H. Stramm
IPC分类号： H04L12/28 , H04L12/56 , G06F9/26
CPC分类号： H04L49/9031 , H04L49/90 , H04L49/901
摘要： A circular buffer storing packets for processing by one or more network processors employs an empty buffer address register identifying where a next received packet should be stored, a next packet address register identifying the next packet to be processed, and a packet-processing address register within each network processor identifying the packet being processed by that network processor. The n-bit addresses to the buffer are mapped or masked from/to the m-bit packet-processing address registers by software, allowing the buffer size to be fully scalable. A dedicated packet retrieval instruction supported by the network processor(s) retrieves a new packet for processing using the next packet address register and copies that into the associated packet-processing address register for use in subsequent accesses. Buffer management is thus independent of the network processor architecture.
摘要翻译：存储用于由一个或多个网络处理器处理的分组的循环缓冲器使用空缓冲器地址寄存器来标识下一个接收到的分组应该被存储在哪里，下一个分组地址寄存器标识下一个待处理分组，以及一个分组处理地址寄存器每个网络处理器识别由该网络处理器正在处理的分组。缓冲区的n位地址由软件映射或掩蔽到m位数据包处理地址寄存器，从而允许缓冲区大小完全可扩展。由网络处理器支持的专用分组检索指令使用下一个分组地址寄存器检索新的分组进行处理，并将其复制到相关的分组处理地址寄存器中以用于随后的访问。因此，缓冲区管理与网络处理器架构无关。

55. 发明授权

US07443878B2 System for scaling by parallelizing network workload 有权
标题翻译：通过并行化网络工作负载进行扩展的系统
公开(公告)号：US07443878B2
公开(公告)日：2008-10-28
申请号：US11098214
申请日：2005-04-04
申请人： Ariel Hendel , Michael Wong , Yatin Gajjar , Shimon Muller
发明人： Ariel Hendel , Michael Wong , Yatin Gajjar , Shimon Muller
IPC分类号： H04L12/66
CPC分类号： H04L47/10 , H04L45/745 , H04L47/2441 , H04L47/27 , H04L47/29 , H04L47/32 , H04L49/90 , H04L49/9031 , H04L49/9063
摘要： A method for scaling a network system which includes providing at least one network interface and providing a flexible association between packets and a plurality of processing entities via the plurality of memory access channels. Each network interface including a plurality of memory access channels.
摘要翻译：一种用于缩放网络系统的方法，其包括提供至少一个网络接口并且经由多个存储器访问信道提供分组与多个处理实体之间的灵活关联。每个网络接口包括多个存储器访问通道。

56. 发明授权

US07362771B1 Reduced latency FIFO 有权
标题翻译：减少延迟FIFO
公开(公告)号：US07362771B1
公开(公告)日：2008-04-22
申请号：US10158337
申请日：2002-05-30
申请人： William Lo , Samuel Er-Shen Tang , Sabu Ghazali
发明人： William Lo , Samuel Er-Shen Tang , Sabu Ghazali
IPC分类号： H04L12/54
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9031
摘要： A First-In-First-Out (FIFO) block to buffer a packet having a size is presented. The FIFO block includes a receiver to receive a data frame including the packet and overhead information, and to extract the packet from the data frame. A buffer has a plurality of memory locations to store the packet in a FIFO configuration. A buffer manager, in response to detecting a buffer low packet condition, stalls reads of the packet from the buffer.
摘要翻译：呈现先进先出（FIFO）块来缓冲具有大小的数据包。 FIFO块包括接收包括分组和开销信息的数据帧的接收器，并从数据帧中提取分组。缓冲器具有多个存储器位置以将数据包存储在FIFO配置中。缓冲器管理器响应于检测到缓冲器低分组条件，停止从缓冲器读取分组。

57. 发明授权

US07299277B1 Media module apparatus and method for use in a network monitoring environment 有权
标题翻译：用于网络监控环境的媒体模块装置和方法
公开(公告)号：US07299277B1
公开(公告)日：2007-11-20
申请号：US10045820
申请日：2002-01-11
申请人： Mike Moran , Tauras Liubinskas , Jack Goral
发明人： Mike Moran , Tauras Liubinskas , Jack Goral
IPC分类号： G06F15/173
CPC分类号： H04L43/028 , H04L41/0213 , H04L41/5022 , H04L43/12 , H04L49/90 , H04L49/901 , H04L49/9031
摘要： A probe apparatus, method and computer program product for application monitoring are provided. A data collection module collects data from a network segment. A flow processor coupled to the data collection module classifies the collected data into a plurality of flows. A capture system coupled to the flow processor filters and buffers the collected data. A main processor processes the filtered data.
摘要翻译：提供了一种用于应用监控的探针设备，方法和计算机程序产品。数据采集模块从网段收集数据。耦合到数据收集模块的流处理器将收集的数据分类成多个流。耦合到流处理器的捕获系统对收集的数据进行滤波和缓冲。主处理器处理过滤后的数据。

58. 发明申请

US20060251108A1 System for scaling by parallelizing network workload 有权
标题翻译：通过并行化网络工作负载进行扩展的系统
公开(公告)号：US20060251108A1
公开(公告)日：2006-11-09
申请号：US11098214
申请日：2005-04-04
申请人： Ariel Hendel , Michael Wong , Yatin Gajjar , Shimon Muller
发明人： Ariel Hendel , Michael Wong , Yatin Gajjar , Shimon Muller
IPC分类号： H04L12/66
CPC分类号： H04L47/10 , H04L45/745 , H04L47/2441 , H04L47/27 , H04L47/29 , H04L47/32 , H04L49/90 , H04L49/9031 , H04L49/9063
摘要： A method for scaling a network system which includes providing at least one network interface and providing a flexible association between packets and a plurality of processing entities via the plurality of memory access channels. Each network interface including a plurality of memory access channels.
摘要翻译：一种用于缩放网络系统的方法，其包括提供至少一个网络接口并且经由多个存储器访问信道提供分组与多个处理实体之间的灵活关联。每个网络接口包括多个存储器访问通道。

59. 发明授权

US07120171B2 Packet data processing apparatus and packet data processing method 失效
公开(公告)号：US07120171B2
公开(公告)日：2006-10-10
申请号：US10091453
申请日：2002-03-07
申请人： Takahiro Sasaki
发明人： Takahiro Sasaki
IPC分类号： H04J3/06
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/9031
摘要： In real time communication, long interruption of a media data signal caused by underflow or overflow of a buffer is reduced. A monitoring unit 35a monitors a state of the buffer 34 periodically. When the number of encoded data in the buffer 34 shows tendency of increasing from a standard data storage number, successively a predetermined number of times, then, it is judged that the buffer tends to overflow. And, the decoding unit 35 is made to skip at least one encoded data to be read and processed this time from the buffer 34. Further, when the number of encoded data in the buffer 34 shows tendency of decreasing from the mentioned standard data storage number, successively the predetermined number of times, then, it is judged that the buffer tends to underflow. And, the processing unit 35 is made to suspend operation during at least one period of the above-mentioned reproduction period.

60. 发明申请

US20060212633A1 Method and system of routing network-based data using frame address notification 有权
标题翻译：使用帧地址通知路由基于网络的数据的方法和系统
公开(公告)号：US20060212633A1
公开(公告)日：2006-09-21
申请号：US11386323
申请日：2006-03-22
申请人： Christian Kasper
发明人： Christian Kasper
IPC分类号： G06F13/24
CPC分类号： H04L49/9021 , H04L49/103 , H04L49/25 , H04L49/254 , H04L49/3009 , H04L49/90 , H04L49/9031 , H04L49/9047 , H04L49/9063 , H04L49/9068
摘要： A method and system for routing network-based data arranged in frames is disclosed. A host processor analyzes transferred bursts of data and initiates an address and look up algorithm for dispatching the frame to a desired destination. A shared system memory existing between a network device, e.g., an HDLC controller, working in conjunction with the host processor, receives data, including any preselected address fields. The network device includes a plurality of ports. Each port includes a FIFO receive memory for receiving at least a first portion of a frame. The first portion of the frame includes data having the preselected address fields. A direct memory access unit transfers a burst of data from the FIFO receive memory to the shared system memory. A communications processor selects the amount of data to be transferred from the FIFO receive memory based on the desired address fields to be analyzed by the host processor.
摘要翻译：公开了一种用于路由布置在帧中的基于网络的数据的方法和系统。主机处理器分析传输的数据突发，并发起一个地址和查找算法，用于将帧发送到所需的目的地。存在于与主处理器结合工作的网络设备（例如，HDLC控制器）之间的共享系统存储器接收包括任何预先选择的地址字段的数据。网络设备包括多个端口。每个端口包括用于接收帧的至少第一部分的FIFO接收存储器。帧的第一部分包括具有预选地址字段的数据。直接存储器访问单元将数据从FIFO接收存储器传送到共享系统存储器。通信处理器基于要由主处理器分析的期望的地址字段来选择要从FIFO接收存储器传送的数据量。

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