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    • 54. 发明申请
    • METHOD AND SYSTEM FOR GENERATING TIMED EVENTS IN A RADIO FRAME IN AN E-UTRA/LTE UE RECEIVER
    • 用于在E-UTRA / LTE UE接收机的无线帧中生成定时事件的方法和系统
    • US20120281792A1
    • 2012-11-08
    • US13480807
    • 2012-05-25
    • Francis SWARTSMark Kent
    • Francis SWARTSMark Kent
    • H04W56/00
    • H04J11/0069H04L27/2663H04L27/2671
    • A mobile device coupled to a common system clock receives a signal comprising a primary synchronization sequence (PSS) and a secondary synchronization sequence (SSS) in a radio frame. Sample counts are generated for timed events based on corresponding operating bandwidths. The timed events are detected at modulo sample counts of the generated sample counts according to corresponding operating bandwidths. PSS symbol timing determined via the PSS synchronization is aligned to the generated sample counts based on corresponding operating bandwidth. The generated sample counts are bit-shifted relative to the aligned PSS symbol timing for other timed events based on corresponding operating bandwidths. The one or more timed events are determined via performing modulo counting after the bit-shifting. Timing operations are performed at the determined timed events and the determined one or more timed events are refined, accordingly.
    • 耦合到公共系统时钟的移动设备在无线电帧中接收包括主同步序列(PSS)和辅同步序列(SSS)的信号。 基于相应的工作带宽为定时事件生成采样计数。 根据相应的工作带宽,以生成的采样计数的模样本计数来检测定时事件。 通过PSS同步确定的PSS符号定时与基于相应的工作带宽的生成的采样计数相对准。 基于对应的工作带宽,生成的采样计数相对于其他定时事件的对准PSS符号定时进行位移。 一个或多个定时事件通过在位移之后执行模计数来确定。 相应地,在确定的定时事件执行定时操作,并且确定所确定的一个或多个定时事件被改进。
    • 56. 发明授权
    • Method and system for generating timed events in a radio frame in an E-UTRA/LTE UE receiver
    • 用于在E-UTRA / LTE UE接收机的无线帧中生成定时事件的方法和系统
    • US08189541B2
    • 2012-05-29
    • US12502196
    • 2009-07-13
    • Francis SwartsMark Kent
    • Francis SwartsMark Kent
    • H04J3/06
    • H04J11/0069H04L27/2663H04L27/2671
    • A mobile device coupled to a common system clock receives a signal comprising a primary synchronization sequence (PSS) and a secondary synchronization sequence (SSS) in a radio frame. Sample counts are generated for timed events based on corresponding operating bandwidths. The timed events are detected at modulo sample counts of the generated sample counts according to corresponding operating bandwidths. PSS symbol timing determined via the PSS synchronization is aligned to the generated sample counts based on corresponding operating bandwidth. The generated sample counts are bit-shifted relative to the aligned PSS symbol timing for other timed events based on corresponding operating bandwidths. The one or more timed events are determined via performing modulo counting after the bit-shifting. Timing operations are performed at the determined timed events and the determined one or more timed events are refined, accordingly.
    • 耦合到公共系统时钟的移动设备在无线电帧中接收包括主同步序列(PSS)和辅同步序列(SSS)的信号。 基于相应的工作带宽为定时事件生成采样计数。 根据相应的工作带宽,以生成的采样计数的模样本计数来检测定时事件。 通过PSS同步确定的PSS符号定时与基于相应的工作带宽的生成的采样计数相对准。 基于对应的工作带宽,生成的采样计数相对于其他定时事件的对准PSS符号定时进行位移。 一个或多个定时事件通过在位移之后执行模计数来确定。 相应地,在确定的定时事件执行定时操作,并且确定所确定的一个或多个定时事件被改进。
    • 57. 发明授权
    • High throughput fine timing
    • 高通量精准时机
    • US08144683B1
    • 2012-03-27
    • US11947746
    • 2007-11-29
    • Qinfang SunKai Shi
    • Qinfang SunKai Shi
    • H04J3/24
    • H04L27/2602H04L25/0202H04L27/2663H04L27/2665H04L27/2675H04L27/2695
    • After detecting the predetermined phase rotation, a receiver can advantageously remove any cyclic shifting delays (CSDs) from the mixed mode packet for each chain. Once any CSDs are removed, the receiver can perform timing offset estimation and decode the mixed mode packet. In another embodiment, a timing offset from a channel for a first chain without any CSDs can be estimated. Compensation for the timing offset in the first chain can then be performed. At this point, the CSDs from other chains can then be removed. After CSD removal, compensation for any timing offsets in the other chains can be performed using the timing offset in the first chain.
    • 在检测到预定的相位旋转之后,接收机可以有利地从每个链路的混合模式分组中去除任何循环移位延迟(CSD)。 一旦任何CSD被去除,接收机可以执行定时偏移估计和解码混合模式分组。 在另一个实施例中,可以估计来自没有任何CSD的第一链的信道的定时偏移。 然后可以执行第一链中的定时偏移的补偿。 在这一点上,可以将其他链的CSD移除。 在CSD去除之后,可以使用第一链中的定时偏移来执行其他链中的任何定时偏移的补偿。
    • 58. 发明申请
    • CORRELATOR AND DEMODULATION DEVICE INCLUDING CORRELATOR
    • 包括相关器的相关器和解调器件
    • US20120051472A1
    • 2012-03-01
    • US13211896
    • 2011-08-17
    • Hiroji AKAHORI
    • Hiroji AKAHORI
    • H04L27/06
    • H04L27/2663H04L27/2691
    • The present invention provides a correlator and a demodulation device including, first and second filter sections having different non-overlapping pass-frequency characteristics, first and second delay circuits that delay the signals output from the first and second filter section by one effective OFDM symbol period, first and second complex conjugate circuits that take the complex conjugates of the delayed signals, first and second complex operation sections that compute the complex-multiplies of the signals from the first and second filter sections and the respective signals for the first and second complex conjugate circuits, first and second moving average processing sections that take moving averages of GI lengths, proportion determination circuit that compares the maximum values of the autocorrelations from each of the first and second moving average processing circuits, and selection-combination circuit that selects the autocorrelation having the largest maximum value based on the comparison result.
    • 本发明提供一种相关器和解调装置,包括具有不同非重叠通过频率特性的第一和第二滤波器部分,第一和第二延迟电路,其将从第一和第二滤波器部分输出的信号延迟一个有效的OFDM符号周期 获取延迟信号的复共轭的第一和第二复共轭电路,计算来自第一和第二滤波器部分的信号的复数乘法的第一和第二复数运算部分以及第一和第二复共轭的相应信号 电路,采取GI长度的移动平均值的第一和第二移动平均处理部分,比较从第一和第二移动平均处理电路中的每一个的自相关的最大值的比例确定电路,以及选择自相关的选择组合电路, 基于t的最大最大值 他比较结果。
    • 59. 发明申请
    • CORRELATOR AND DEMODULATION DEVICE INCLUDING THE CORRELATOR
    • 包括相关器的相关器和解调器件
    • US20120045004A1
    • 2012-02-23
    • US13210099
    • 2011-08-15
    • Hiroji AKAHORI
    • Hiroji AKAHORI
    • H04K1/10H04L27/06
    • H04L27/2663H04L27/2671H04L27/2678H04L27/2688
    • The Present invention provides a correlator including, a read-out processing circuit that reads out an OFDM signal in RAM as 2n−1 number of delay OFDM signals that are increased and delayed sequentially with their adjusted read-out timings. Complex conjugate circuits that outputs complex conjugates of the inputted nth to 2n−1th delay OFDM signals. Complex arithmetic circuits that perform complex multiplication to inputted original OFDM signal, the first to n−1th delay OFDM signals, and the output signals from the complex conjugate circuits. Moving average processing circuits take the moving average of the GI length, gain adjustment circuits adjust the gains, an adder circuit adds the outputs of the adjustment circuits, and a filter circuit smoothes the addition result. A control circuit variably controls the delay of the delay OFDM signals, the gains of the gain adjustment circuits, and the band characteristic of the filter circuit.
    • 本发明提供了一种相关器,其包括:读出处理电路,其读出RAM中的OFDM信号,作为2n-1个延迟OFDM信号,并按其调整后的读出时序顺序增加和延迟。 输出第n至第2n延迟OFDM信号的复共轭的复共轭电路。 对输入的原始OFDM信号执行复数乘法的复数运算电路,第一至第n延迟OFDM信号和来自复共轭电路的输出信号。 移动平均处理电路采用GI长度的移动平均值,增益调整电路调整增益,加法器电路将调整电路的输出相加,滤波器电路平滑相加结果。 控制电路可变地控制延迟OFDM信号的延迟,增益调整电路的增益以及滤波器电路的频带特性。