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51. 发明申请

US20110064123A1 MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER 有权
标题翻译：多对数字万用表以太网收发器
公开(公告)号：US20110064123A1
公开(公告)日：2011-03-17
申请号：US12849528
申请日：2010-08-03
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H04B1/38
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

52. 发明申请

US20110007793A1 JOINT TIME/FREQUENCY PROCESSING FOR WIRELESS RECEIVERS 有权
标题翻译：无线接收器的联合时间/频率处理
公开(公告)号：US20110007793A1
公开(公告)日：2011-01-13
申请号：US12500891
申请日：2009-07-10
申请人： Douglas A. Cairns , Andres Reial , Anders Wallen
发明人： Douglas A. Cairns , Andres Reial , Anders Wallen
IPC分类号： H04L27/01
CPC分类号： H04L25/03261 , H04L25/03235
摘要： Channel estimation and/or equalization processing is performed in a wireless receiver in two stages. The first stage involves pre-filtering in the frequency domain to compact a grid-based representation of the net channel. The second stage involves implementing reduced-complexity time domain channel estimation and/or equalization. According to one embodiment, a received signal transmitted over a net channel is processed by pre-filtering the received signal in the frequency domain. The frequency domain pre-filtering compacts an N-tap effective grid-based representation of the net channel into a K-tap compacted grid-based representation of the net channel where K
摘要翻译：信道估计和/或均衡处理在两个阶段中在无线接收机中执行。第一阶段涉及在频域中进行预滤波以压缩网络通道的基于网格的表示。第二阶段涉及实现降低复杂度的时域信道估计和/或均衡。根据一个实施例，通过净频道发送的接收信号通过对频域中的接收信号进行预滤波来处理。频域预滤波将网络通道的N抽头有效网格表示压缩为K

53. 发明授权

US07852915B2 Adaptive equalizer for communication channels 有权
标题翻译：用于通信信道的自适应均衡器
公开(公告)号：US07852915B2
公开(公告)日：2010-12-14
申请号：US11726318
申请日：2007-03-21
申请人： Weizhong Chen
发明人： Weizhong Chen
IPC分类号： H03H7/30
CPC分类号： H04L25/03038 , H04L25/03133 , H04L25/03235 , H04L25/03261 , H04L27/2273 , H04L2025/03401 , H04L2025/03407 , H04L2025/03426 , H04L2025/03617 , H04L2027/0028 , H04L2027/0057 , H04L2027/0065
摘要： Adaptive equalizers for a communication channel and corresponding methods of equalizing are described. The adaptive equalizer includes: a fixed pre-filter configured to be coupled to a received signal and provide a pre-filter signal; an adaptive filter coupled to and configured to compensate the pre-filter signal for changes in phase and amplitude; and an interference remover coupled to the adaptive filter and configured to reduce interference in the received signal.
摘要翻译：描述了用于通信信道的自适应均衡器和相应的均衡方法。自适应均衡器包括：固定预滤波器，其被配置为耦合到接收信号并提供预滤波器信号; 耦合到并且被配置为补偿预滤波器信号以用于相位和幅度变化的自适应滤波器; 以及耦合到所述自适应滤波器并被配置为减少所述接收信号中的干扰的干扰去除器。

54. 发明授权

US07801241B2 Multi-pair gigabit Ethernet transceiver 失效
标题翻译：多对千兆以太网收发器
公开(公告)号：US07801241B2
公开(公告)日：2010-09-21
申请号：US12534614
申请日：2009-08-03
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H04B5/00
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

55. 发明授权

US07792186B2 Multi-pair gigabit ethernet transceiver having a single-state decision feedback equalizer 失效
标题翻译：具有单态判决反馈均衡器的多对千兆以太网收发器
公开(公告)号：US07792186B2
公开(公告)日：2010-09-07
申请号：US11692091
申请日：2007-03-27
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

56. 发明授权

US07733952B2 Multi-pair gigabit Ethernet transceiver having adaptive disabling of circuit elements 有权
标题翻译：具有电路元件自适应禁用的多对千兆以太网收发器
公开(公告)号：US07733952B2
公开(公告)日：2010-06-08
申请号：US11688683
申请日：2007-03-20
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

57. 发明授权

US07702991B2 Method and apparatus for reduced-state viterbi detection in a read channel of a magnetic recording system 有权
标题翻译：在磁记录系统的读通道中进行简化状态维特比检测的方法和装置
公开(公告)号：US07702991B2
公开(公告)日：2010-04-20
申请号：US11691847
申请日：2007-03-27
申请人： Erich Franz Haratsch
发明人： Erich Franz Haratsch
IPC分类号： H03M13/03
CPC分类号： G11B20/18 , G11B2020/1863 , H03M13/41 , H04L25/03191 , H04L25/03235
摘要： A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback in magnetic recording systems. A read channel signal is processed in a magnetic recording device by precomputing branch metrics, intersymbol interference estimates or intersymbol interference-free signal estimates for speculative sequences of one or more channel symbols; selecting one of the precomputed values based on at least one decision from at least one corresponding state; and selecting a path having a best path metric for a given state.
摘要翻译：公开了一种用于通过磁记录系统中的局部反馈来提高降维态维特比检测器的最大数据速率的方法和装置。通过预先计算一个或多个信道符号的推测序列的分支度量，符号间干扰估计或符号间无干扰信号估计，在磁记录装置中处理读通道信号; 基于来自至少一个对应状态的至少一个决定来选择预计算值之一; 以及为给定状态选择具有最佳路径度量的路径。

58. 发明申请

US20100091832A1 PIPELINED DECISION-FEEDBACK UNIT IN A REDUCED-STATE VITERBI DETECTOR WITH LOCAL FEEDBACK 审中-公开
标题翻译：在具有本地反馈的减少状态VITERBI检测器中的管理决策反馈单元
公开(公告)号：US20100091832A1
公开(公告)日：2010-04-15
申请号：US12640590
申请日：2009-12-17
申请人： Erich Franz Haratsch
发明人： Erich Franz Haratsch
IPC分类号： H04B1/10 , H03H7/30
CPC分类号： H04L25/03235 , H03M13/03 , H04L25/03057 , H04L25/4917
摘要： A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interfence-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.
摘要翻译：公开了一种流水线判决反馈单元（DFU），用于具有本地反馈的简化状态维特比检测器。所公开的流水线判决反馈单元通过基于部分符号间距的估计的流水线计算提高了通过简化状态维特比检测器可以实现的最大数据速率。因此公开了流水线判决反馈单元，其计算多个基于部分符号间干扰的估计，其中至少一个部分符号间干扰估计基于所选择的部分符号间干扰估计; 并且将所选择的部分符号间干扰估计从用于路径扩展的部分符号间干扰估计中选择为状态。

59. 发明授权

US07653868B2 Method and apparatus for precomputation and pipelined selection of branch metrics in a reduced state Viterbi detector 失效
标题翻译：用于在还原状态Viterbi检测器中进行预计算和流水线选择分支度量的方法和装置
公开(公告)号：US07653868B2
公开(公告)日：2010-01-26
申请号：US12101322
申请日：2008-04-11
申请人： Erich Franz Haratsch
发明人： Erich Franz Haratsch
IPC分类号： H03M13/03
CPC分类号： H04L25/03235 , G11B20/10296 , H03M13/41
摘要： A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback. The maximum data rate that may be achieved by the disclosed reduced state Viterbi detectors is improved by precomputing a number of candidate branch metrics and performing pipelined selection of an appropriate branch metric. A reduced state Viterbi detector is thus disclosed that precomputes branch metrics for speculative sequences of one or more channel symbols; selects one of said precomputed branch metrics based on at least one decision from at least one corresponding state using at least two pipeline registers; and selects a path having a best path metric for a given state.
摘要翻译：公开了一种用于利用本地反馈来提高降维态维特比检测器的最大数据速率的方法和装置。通过预先计算多个候选分支度量并执行适当的分支度量的流水线选择来改进由公开的减少状态维特比检测器可以实现的最大数据速率。因此，公开了一种缩减状态维特比检测器，其预先计算一个或多个信道符号的推测序列的分支度量; 基于使用至少两个流水线寄存器的至少一个对应状态的至少一个判定来选择所述预计算分支度量中的一个; 并为给定状态选择具有最佳路径度量的路径。

60. 发明申请

US20090285342A1 PERTURBED DECODER, PERTURBED DECODING METHOD AND APPARATUS IN COMMUNICATION SYSTEM USING THE SAME 有权
标题翻译： PERTURBED DECODER，PERTURBED DECODING METHOD AND APPARATUS IN COMMUNICATION SYSTEM WITH THE SAME
公开(公告)号：US20090285342A1
公开(公告)日：2009-11-19
申请号：US12120212
申请日：2008-05-13
申请人： Jung Hoon SUH , Sung Jin KIM , David J. LOVE , Obadamilola Aluko , James V. Krogmeier
发明人： Jung Hoon SUH , Sung Jin KIM , David J. LOVE , Obadamilola Aluko , James V. Krogmeier
IPC分类号： H04B1/10
CPC分类号： H04B7/0452 , H04L25/03235 , H04L25/03242 , H04L25/03254 , H04L25/03318 , H04L25/03331 , H04L25/03891 , H04L25/03968 , H04L2025/03426 , H04L2025/03624
摘要： A decoder adopted to receive a signal transmitted in a communication system, includes one or more of a module adopted to pre-process a received signal to reduce the effect of interference-plus-noise on the received signal before filtering the received signal, and a module adopted to post-process the result of filtering the received signal.
摘要翻译：用于接收在通信系统中发送的信号的解码器包括在对接收信号进行滤波之前预处理接收信号以减少干扰加噪声对接收信号的影响的模块中的一个或多个，以及模块采用后处理滤波接收信号的结果。

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