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51. 发明申请

US20070195949A1 Encryption processing method and encryption processing device 有权
标题翻译：加密处理方法和加密处理装置
公开(公告)号：US20070195949A1
公开(公告)日：2007-08-23
申请号：US11653879
申请日：2007-01-17
申请人： Toshio Okochi , Takashi Endo , Takashi Watanabe , Tatsuya Kameyama , Shunsuke Ota
发明人： Toshio Okochi , Takashi Endo , Takashi Watanabe , Tatsuya Kameyama , Shunsuke Ota
IPC分类号： H04L9/28
CPC分类号： H04L9/003 , G06F21/72 , G06F21/75 , G06F21/755 , H04L2209/122
摘要： An increase in safety from attacks by use of hardware-like methods by small-sized hardware is achieved. An encryption processing device includes a logical circuit capable of programmably setting logics for executing cipher processing, a memory that stores plural pieces of logical configuration information corresponding to an identical cipher processing algorithm, and a CPU that selectively sets plural logics corresponding to an identical cipher processing algorithm in the logical circuit. Even in processing using an identical cipher key, by changing the logic of the logical circuit for each processing, power consumption in cipher processing can be varied, and places a timing in which malfunctions occur can be varied. Moreover, an increase in the scale of hardware for realizing plural logics can be curbed.
摘要翻译：实现了通过使用小型硬件的类似硬件的方法的攻击来提高安全性。加密处理装置包括能够可编程地设置用于执行密码处理的逻辑的逻辑电路，存储与相同密码处理算法相对应的多条逻辑配置信息的存储器，以及选择性地设置与相同的密码处理对应的多个逻辑的CPU 算法在逻辑电路中。即使在使用相同的加密密钥的处理中，通过改变每个处理的逻辑电路的逻辑，可以改变密码处理中的功耗，并且可以改变发生故障的定时。此外，可以抑制用于实现多个逻辑的硬件规模的增加。

52. 发明申请

US20060198524A1 Hardware implementation of the mixcolumn/invmiscolumn functions 审中-公开
标题翻译： mixcolumn / invmiscolumn函数的硬件实现
公开(公告)号：US20060198524A1
公开(公告)日：2006-09-07
申请号：US10556329
申请日：2004-05-10
申请人： Bonnie Sexton
发明人： Bonnie Sexton
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , H04L2209/122 , H04L2209/125 , H04L2209/80
摘要： An encryption/decryption unit, a conversion module, a method and a computer program product share common logic for both a cipher transformation and an inverse cipher transformation to reduce the number of gates requires with a small increase in wait time. A keyschedule unit providing at least one key value. The conversion module, which is in communication with the keyschedule unit, converts a block of plain text/ciphered text into a predetermined number of byte units in a first plurality of columns. The conversion module includes a MixColumnAll submodule that utilizes shared circuitry for both a transformation of a cipher function to produce a second plurality of columns from the first plurality of columns, and for an inverse cipher function to produce the first plurality of columns from the second plurality of columns. The MixColumnAll submodule performs a combined MixColumn and InvMixColumn that are performed in AES. A block round unit for encrypting/decrypting the predetermined number of byte units into ciphered text/plain text.
摘要翻译：加密/解密单元，转换模块，方法和计算机程序产品共享用于密码变换和逆密码变换的公共逻辑以减少门数需要等待时间的小的增加。提供至少一个键值的键调度单元。与密钥调度单元通信的转换模块将明文/加密文本块在第一多个列中转换成预定数量的字节单位。该转换模块包括一个MixColumnAll子模块，它利用共享电路来进行加密函数的变换以从第一多个列产生第二多个列，以及使用反向密码函数从第二多个列产生第一多个列的列。 MixColumnAll子模块执行AES中执行的组合MixColumn和InvMixColumn。用于将预定数量的字节单元加密/解密为加密文本/纯文本的块循环单元。

53. 发明申请

US20060072746A1 Register scheduling in iterative block encryption to reduce memory operations 审中-公开
标题翻译：在迭代块加密中注册调度以减少内存操作
公开(公告)号：US20060072746A1
公开(公告)日：2006-04-06
申请号：US10953864
申请日：2004-09-28
申请人： Hari Tadepalli
发明人： Hari Tadepalli
IPC分类号： H04K1/06
CPC分类号： H04L9/0631 , H04L2209/122
摘要： Systems and methods encrypt data according to a multi-round, block encryption algorithm, In some embodiments, each round includes transforming data held in a group of registers of a processor register set and maintaining round output in the group of registers to use as input in a subsequent round. In some embodiments, the multi-round, block encryption algorithm is the Advanced Encryption Standard algorithm.
摘要翻译：系统和方法根据多轮，块加密算法对数据进行加密。在一些实施例中，每轮包括变换保存在处理器寄存器组的寄存器组中的数据，并保持该组寄存器中的循环输出以用作输入随后一轮。在一些实施例中，多循环块加密算法是高级加密标准算法。

54. 发明申请

US20060050873A1 Block cipher apparatus using auxiliary transformation 有权
标题翻译：使用辅助转换的块密码设备
公开(公告)号：US20060050873A1
公开(公告)日：2006-03-09
申请号：US11260126
申请日：2005-10-28
申请人： Mitsuru Matsui , Toshio Tokita , Junko Nakajima , Masayuki Kanda , Shiho Moriai , Kazumaro Aoki
发明人： Mitsuru Matsui , Toshio Tokita , Junko Nakajima , Masayuki Kanda , Shiho Moriai , Kazumaro Aoki
IPC分类号： H04K1/06
CPC分类号： H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL−1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL−1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.
摘要翻译：期望由加密单元200和解密单元500共享一个电路。正常数据变换单元（FL）251和逆数据变换单元（FL <-1> ）273位于点在非线性数据变换单元220上的对称性以及正常数据变换单元（FL）253和逆数据变换单元（FL_AND1）271位于非线性数据变换单元220上的点对称数据变换单元220.因此，加密单元200和解密单元500可以使用相同的电路来配置。

55. 发明申请

US20060050872A1 Block cipher apparatus using auxiliary transformation 有权
公开(公告)号：US20060050872A1
公开(公告)日：2006-03-09
申请号：US11260110
申请日：2005-10-28
申请人： Mitsuru Matsui , Toshio Tokita , Junko Nakajima , Masayuki Kanda , Shiho Moriai , Kazumaro Aoki
发明人： Mitsuru Matsui , Toshio Tokita , Junko Nakajima , Masayuki Kanda , Shiho Moriai , Kazumaro Aoki
IPC分类号： H04K1/06
CPC分类号： H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL−1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL−1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

56. 发明申请

US20060020822A1 Device and method for calculating encrypted data from unencrypted data or unencrypted data from encrypted data 审中-公开
标题翻译：从加密数据计算加密数据或加密数据的未加密数据的装置和方法
公开(公告)号：US20060020822A1
公开(公告)日：2006-01-26
申请号：US11193038
申请日：2005-07-29
申请人： Manfred Aigner , Holger Bock
发明人： Manfred Aigner , Holger Bock
IPC分类号： G06F12/14 , H04L9/32 , G06F11/30 , G06F11/00 , G06F11/22 , G06F11/32 , G06F11/34 , G06F11/36 , G06F12/16 , G06F15/18 , G08B23/00
CPC分类号： H04L9/0625 , H04L9/003 , H04L2209/122
摘要： In a device for calculating encrypted data from plaintext data or plaintext data from encrypted data, in which a cryptographic algorithm having an initial stage, an intermediate stage or final stage and an intermediate stage upstream of the final stage is implemented, the processor for performing the cryptographic algorithm is formed such that it performs either the initial stage or the final stage or both the initial stage and the final stage in a manner protected against a cryptographic attack, whereas the intermediate stage is performed in a manner unprotected against a cryptographic attack.
摘要翻译：在用于从加密数据中从明文数据或明文数据计算加密数据的装置中，其中实现了具有初始阶段，中间阶段或最后阶段以及最后阶段上游的中间阶段的密码算法，用于执行形成加密算法，使得其以保护密码攻击的方式执行初始阶段或最后阶段，或初始阶段和最后阶段，而中间阶段以不受加密攻击的保护方式执行。

57. 发明申请

US20040260740A1 System and method of efficiently implementing secure hash algorithm (SHA-1) in digital hardware that accomplishes optimal computation speed using minimal hardware resources 有权
标题翻译：在数字硬件中有效实现安全散列算法（SHA-1）的系统和方法，使用最少的硬件资源实现最佳计算速度
公开(公告)号：US20040260740A1
公开(公告)日：2004-12-23
申请号：US10704678
申请日：2003-11-12
发明人： Yen-Fu Liu
IPC分类号： G06F007/38
CPC分类号： H04L9/0643 , H04L2209/122
摘要： A method of completing the Secure Hash Algorithm (SHA-1) computation in exactly 81 clock cycles with digital hardware. The general implementation techniques include: using a combination of synchronous storage elements to store the required computation values and asynchronous circuits to perform all the logic and mathematic operations of each step of the 81-step SHA-1 computation within a single clock cycle; using a quad-output-channel 16null32-bit circular queue memory to store the 512-bit message segment (block), as a computation buffer of the Wt parameter, and to supply the Wt-3, Wt-8, Wt-14, and Wt-16 data parameters simultaneously; using a combination of a counter circuit and a decoder/encoder circuit to control selecting data parameters and sequencing the 81-step SHA-1 computation; and using an automated controller to control internal units that perform SHA-1 and allowing external systems to access the SHA-1 computation service. The robust architecture allows for a highly efficient digital hardware implementation.
摘要翻译：用数字硬件完成81个时钟周期的安全散列算法（SHA-1）计算的方法。一般实现技术包括：使用同步存储元件的组合来存储所需的计算值和异步电路，以在单个时钟周期内执行81步骤SHA-1计算的每个步骤的所有逻辑和数学运算; 使用四输出通道16x32位循环队列存储器存储512位消息段（块）作为Wt参数的计算缓冲区，并提供Wt-3，Wt-8，Wt-14，和Wt-16数据参数; 使用计数器电路和解码器/编码器电路的组合来控制选择数据参数并对81步SHA-1计算进行排序; 并使用自动控制器来控制执行SHA-1的内部单元，并允许外部系统访问SHA-1计算服务。坚固的架构允许高效的数字硬件实现。

58. 发明申请

US20040184607A1 CRYPTO-SYSTEM WITH AN INVERSE KEY EVALUATION CIRCUIT 审中-公开
标题翻译：具有反向关键评估电路的CRYPTO系统
公开(公告)号：US20040184607A1
公开(公告)日：2004-09-23
申请号：US10605540
申请日：2003-10-07
发明人： Chih-Pen Chang , Ming-Shiang Lai
IPC分类号： H04L009/00
CPC分类号： H04L9/0631 , H04L2209/122
摘要： An inverse key evaluation circuit for inversely generating a plurality of pre-keys in sequence according to an original key, and a crypto-system containing the inverse key evaluation circuit for decrypting a ciphered text into a plain text according to the plurality of pre-keys. The inverse key evaluation circuit includes a key-receiving module and an inverse key evaluation module. The key-receiving module includes a register for temporally receiving and storing the original key, which will be processed by the inverse key evaluation module to generate the plurality of pre-keys of the original key. The key stored in the register will then be replaced by the newly generated pre-key in sequence. The crypto-system includes a key-generating module that contains the inverse key evaluation circuit, an encryption module, and a decryption module.
摘要翻译：一种用于根据原始密钥依次反向生成多个预密钥的反向键评估电路，以及包含用于根据多个预密钥将加密文本解密为纯文本的反向键评估电路的密码系统。逆键评估电路包括键接收模块和反键评估模块。密钥接收模块包括用于临时接收和存储原始密钥的寄存器，该原始密钥将由反向密钥评估模块处理，以生成原始密钥的多个预密钥。存储在寄存器中的密钥将被新生成的预密钥依次替换。密码系统包括包含反向键评估电路的密钥生成模块，加密模块和解密模块。

59. 发明申请

US20030046561A1 Non-algebraic cryptographic architecture 审中-公开
标题翻译：非代数密码体系结构
公开(公告)号：US20030046561A1
公开(公告)日：2003-03-06
申请号：US10231608
申请日：2002-08-30
发明人： Jon W. Hamilton
IPC分类号： G06F012/14
CPC分类号： H04L9/0637 , H04L9/0838 , H04L2209/122 , H04L2209/125 , H04N1/32144 , H04N1/32208 , H04N1/32309 , H04N2201/3226 , H04N2201/3233 , H04N2201/327 , H04N2201/3271
摘要： A non-algebraic cryptographic architecture. The non-algebraic cryptographic architecture is a logical implementation of a non-algebraic cryptographic engine (sometimes referred to as a nullNACEnull). The architecture uses a NACE in conjunction with cryptographic key lengths up to 2048 bits to achieve real-time encryption at speeds sufficient to permit wideband digital data to be decrypted in real time thereby obviating the need for store-and-forward. The architecture is inherently parallel and can accept extended block lengths, which are several multiples of the length of the cryptographic key.
摘要翻译：非代数密码体系结构。非代数加密架构是非代数加密引擎（有时称为“NACE”）的逻辑实现。该架构使用NACE与高达2048位的加密密钥长度来实现实时加密，速度足以允许实时解密宽带数字数据，从而避免了存储转发的需要。架构本质上是并行的，并且可以接受扩展块长度，这是加密密钥长度的几倍。

60. 发明授权

US5740251A Data processing apparatus 失效
标题翻译：数据处理装置
公开(公告)号：US5740251A
公开(公告)日：1998-04-14
申请号：US428364
申请日：1995-04-25
申请人： Masato Tajima , Taro Shibagaki
发明人： Masato Tajima , Taro Shibagaki
IPC分类号： H04L9/06 , H04L9/00 , H04L9/28
CPC分类号： H04L9/0618 , H04L9/0643 , H04L2209/046 , H04L2209/122 , H04L2209/30
摘要： A block processing section divides message data into a plurality of blocks, so as to obtain a plurality of data blocks. A plurality of data encryption processing sections are provided in correspondence to the data blocks. The first one of the data encryption processing sections selects one of pre-stored data conversion algorithms in response to an initial selection control signal. Each of the remaining data encryption processing sections selects one of the data conversion algorithms in response to a selection control signal supplied from a preceding data encryption processing section. Each of the data encryption processing sections performs data encryption processing with respect to the corresponding data block on the basis of the selected data conversion algorithm, and generates a selection control signal to be supplied to the succeeding data encryption processing section, on the basis of the data obtained by the data encryption processing.
摘要翻译：块处理部将消息数据分割成多个块，以获得多个数据块。对应于数据块提供多个数据加密处理部分。第一个数据加密处理部分响应初始选择控制信号选择一个预先存储的数据转换算法。每个剩余数据加密处理部分响应于从先前数据加密处理部分提供的选择控制信号来选择一个数据转换算法。每个数据加密处理部分基于所选择的数据转换算法对相应的数据块执行数据加密处理，并且基于所选择的数据转换算法生成提供给后续数据加密处理部分的选择控制信号通过数据加密处理得到的数据。

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