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    • 52. 发明申请
    • SEMICONDUCTOR MEMORY, SEMICONDUCTOR MEMORY SYSTEM, AND ERROR CORRECTION METHOD FOR SEMICONDUCTOR MEMORY
    • SEMICONDUCTOR MEMORY,SEMICONDUCTOR MEMORY SYSTEM,AND ERROR CORRECTION METHOD FOR SEMICONDUCTOR MEMORY
    • US20080301519A1
    • 2008-12-04
    • US12127603
    • 2008-05-27
    • Kuninori KAWABATA
    • Kuninori KAWABATA
    • H03M13/11G06F11/10
    • H03M13/2915G06F11/1008G06F11/108H03M13/19H03M13/2906
    • Aspects of the embodiment include providing a semiconductor memory comprising; a plurality of memory blocks that includes a plurality of regular memory cells; a plurality of first parity blocks that are disposed in accordance with the plurality of memory blocks, wherein the plurality of first parity blocks include a first parity memory cell holding a first parity code; a second parity block that includes a second parity memory cell holding a second parity code having a parity bit corresponding to the first parity code; a parity error correction unit that corrects an error of the first parity code using the second parity code; and a data error correction unit that corrects an error of the data stored in a regular memory cell using the first parity code corrected by the parity error correction unit.
    • 实施例的方面包括提供半导体存储器,包括: 多个存储块,包括多个常规存储单元; 多个第一奇偶校验块,其根据所述多个存储块设置,其中所述多个第一奇偶校验块包括保持第一奇偶校验码的第一奇偶校验存储单元; 第二奇偶校验块,包括保持具有对应于第一奇偶校验码的奇偶校验位的第二奇偶校验码的第二奇偶校验存储单元; 奇偶纠错单元,其使用所述第二奇偶校验码校正所述第一奇偶码的误差; 以及数据误差校正单元,其使用由奇偶纠错单元校正的第一奇偶校验来校正存储在常规存储单元中的数据的误差。
    • 53. 发明申请
    • Error detection detection device and error detection method
    • 错误检测装置和错误检测方法
    • US20070033506A1
    • 2007-02-08
    • US10569960
    • 2004-08-19
    • Syuji MatsudaHiroyuki Yabuno
    • Syuji MatsudaHiroyuki Yabuno
    • H03M13/00
    • G11B20/1833G11B20/1803G11B2020/184G11B2220/2562H03M13/03H03M13/29H03M13/2909H03M13/2915
    • In an error detection method of the present invention, as shown in FIG. 1, target code strings which are inputted in a discontinuous arrangement are subjected to a syndrome operation, and simultaneously, the target code strings which are inputted in a discontinuous arranged are subjected to a first error detection code operation while correcting the inter-data continuity by skipping the data so that the arrangement of the code strings have continuity. Then, error data positions and error data numerical values of the target code strings are calculated on the basis of a syndrome obtained in the syndrome operation, and only the error data position among the target code strings are subjected to a second error detection code operation again on the basis of the error data positions and the error data numerical values. Using the operation result, the operation result by the first error detection code operation is updated, thereby simultaneously performing ECC processing and EDC processing for the target code strings which are inputted in a discontinuous arrangement.
    • 在本发明的错误检测方法中, 如图1所示,以不连续的方式输入的目标代码串被进行校正子操作,同时,以不连续的方式输入的目标代码串经过第一错误检测代码操作,同时通过 跳过数据,使代码串的排列具有连续性。 然后,基于在校正子操作中获得的校正子来计算目标代码串的误差数据位置和误差数据数值,并且仅对目标代码串中的误差数据位置再次进行第二错误检测码操作 基于误差数据位置和误差数据数值。 使用运算结果,更新第一检错码运算的运算结果,同时对不连续配置输入的目标代码串进行ECC处理和EDC处理。
    • 56. 发明授权
    • Packet transmitter
    • 包发送器
    • US06826181B1
    • 2004-11-30
    • US09214830
    • 1999-03-10
    • Masaaki HigashidaYoshihiro MoriokaMasakazu NishinoSatoshi OhyamaMasaaki Kobayashi
    • Masaaki HigashidaYoshihiro MoriokaMasakazu NishinoSatoshi OhyamaMasaaki Kobayashi
    • H04L1228
    • H03M13/2915H03M13/09H03M13/1515H03M13/2707H04L12/5601H04L49/557H04L49/90H04L49/901H04L2012/5618H04L2012/5627H04L2012/5647H04L2012/5652H04L2012/5653H04L2012/5664H04N21/2381H04N21/64307H04Q11/0478
    • There is disclosed a packet transmission apparatus for transmitting in a packet form a transmission unit including a data string arranged so as to divide predetermined data into a plurality of blocks, each block having a fixed length, block information for specifying the block type being added to each block. A DIF data processing circuit generates a transmission header having a new identifier by deleting predetermined redundancy information from the block information belonging to the plurality of blocks based on inputted data string, and then, generates a transmission unit having the generated transmission header. Next, a transmission terminal unit transmits the generated transmission unit by way of a transmission line. In this case, the DIF data processing circuit generates a new identifier by making the information of one block represent the information of the plurality of blocks to generate a transmission header having the generated identifier, or making the information of one block represent the information of an identical block or deleting the redundancy information including at least one of reserved data and invalid data.
    • 公开了一种分组发送装置,用于以分组形式发送包括数据串的发送单元,所述发送单元被布置为将预定数据划分为多个块,每个块具有固定长度,用于指定块类型的块信息被添加到 每个块。 DIF数据处理电路根据输入的数据串,从属于多个块的块信息中删除预定的冗余信息,生成具有新标识符的发送报头,生成具有生成的发送报头的发送单元。 接下来,发送终端单元通过传输线发送生成的发送单元。 在这种情况下,DIF数据处理电路通过使一个块的信息表示多个块的信息来生成具有生成的标识符的发送报头,生成新的标识符,或者使一个块的信息表示信息 相同的块或删除包括保留数据和无效数据中的至少一个的冗余信息。