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51. 发明授权

US09083366B1 Alignment of sampling phases in a multi-channel time-interleaved analog-to-digital converter 有权
标题翻译：多通道时间交织模数转换器中采样相位的对准
公开(公告)号：US09083366B1
公开(公告)日：2015-07-14
申请号：US14220257
申请日：2014-03-20
申请人： LSI Corporation
发明人： Viswanath Annampedu , Amaresh V. Malipatil
IPC分类号： H03M1/12 , H03M1/08 , H03M1/18
CPC分类号： H03M1/0836 , H03M1/1215 , H04L7/002 , H04L7/0058 , H04L7/0087 , H04L7/0331
摘要： A multi-channel analog-to-digital (ADC) converter coupled to a clock-and-data-recovery loop that has a plurality of clock-recovery circuits, each configured to set the sampling phase for a respective one of the ADC channels in a manner that causes the different sampling phases to be appropriately time-aligned with one another for time-interleaved operation of the ADC channels. In an example embodiment, an individual clock-recovery circuit comprises a phase detector and a loop filter. Loop filters corresponding to different clock-recovery circuits may be coupled to one another by having shared circuit elements in their frequency-tracking paths and/or by being configured to receive timing gradients from more than one phase detector, including the phase detector of a selected one of the clock-recovery circuits.
摘要翻译：耦合到时钟和数据恢复环路的多通道模数（ADC）转换器，其具有多个时钟恢复电路，每个时钟恢复电路被配置为将ADC通道中的相应一个通道的采样相位设置在使得不同采样相位彼此适当地时间对准以便ADC通道的时间交替操作的方式。在示例实施例中，单独的时钟恢复电路包括相位检测器和环路滤波器。对应于不同时钟恢复电路的环路滤波器可以通过在其频率跟踪路径中具有共享电路元件和/或通过被配置为从多于一个的相位检测器接收定时梯度来彼此耦合，包括所选择的相位检测器其中一个时钟恢复电路。

52. 发明授权

US09076554B1 Low-noise low-distortion signal acquisition circuit and method with reduced area utilization 有权
标题翻译：低噪声低失真信号采集电路和方法，减少面积利用率
公开(公告)号：US09076554B1
公开(公告)日：2015-07-07
申请号：US14260885
申请日：2014-04-24
申请人： Aeroflex Colorado Springs Inc.
发明人： Alfio Zanchi , Shinichi Hisano
IPC分类号： G11C27/02 , H03F3/45 , H03M1/36
CPC分类号： G11C27/026 , H01L31/02002 , H03F1/08 , H03F1/083 , H03F3/08 , H03F3/087 , H03F3/45076 , H03F3/45475 , H03F2200/129 , H03F2200/156 , H03F2200/45 , H03F2203/45444 , H03F2203/45514 , H03M1/1215
摘要： A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.
摘要翻译：采样和保持放大器包括用于接收输入电流信号的输入节点，具有耦合到输入节点的输入的非线性采样电容器电路，具有耦合到非线性采样电容器的输出的负输入的运算放大器电路，耦合到地的正输入，以及用于提供采样和保持电压信号的输出，以及耦合在运算放大器的负输入和输出之间的线性电容器。非线性采样电容器包括耦合在中间节点和地之间的非线性电容器，耦合在被配置为根据第一相位信号切换的输入和中间节点之间的第一开关，以及耦合在输出和所述中间节点被配置为根据第二相位信号进行切换。

53. 发明授权

US09071270B2 Time-interleaved analog-to-digital converter bandwidth matching 有权
标题翻译：时间交织的模数转换器带宽匹配
公开(公告)号：US09071270B2
公开(公告)日：2015-06-30
申请号：US13906590
申请日：2013-05-31
申请人： Crest Semiconductors, Inc
发明人： Tracy Johancsik , Ryan James Kier , Yusuf Haque
IPC分类号： H03M1/00 , H03M1/54 , H03M1/10 , H03M1/12
CPC分类号： H03M1/54 , H03M1/1061 , H03M1/1215 , H03M1/1245
摘要： A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.
摘要翻译：时间交织的模数转换器（ADC）包括一组时间多路复用子ADC电路，每个子ADC电路包括采样和保持电路。每个采样和保持电路包括一个自举电路，用于在开关的输入端和开关的栅极端之间保持恒定的电压电平，用于在轨道模式和保持模式之间切换的开关以及电容器组相关联其中自举电路使得电容器组的设置影响电压电平。

54. 发明授权

US09041573B2 Sampling device with buffer circuit for high-speed ADCs 有权
标题翻译：具有高速ADC缓冲电路的采样器
公开(公告)号：US09041573B2
公开(公告)日：2015-05-26
申请号：US14217710
申请日：2014-03-18
申请人： International Business Machines Corporation
发明人： Lukas Kull , Thomas H Toifl
IPC分类号： H03M1/00 , H03M1/12 , H03M1/68
CPC分类号： H03M1/121 , G11C27/02 , H03M1/1215 , H03M1/1245 , H03M1/685
摘要： A sampling and interleaving stage device for use in an analog-digital-converter and for providing a sampling output signal and an analog-to-digital-converter. The sampling and interleaving stage device for use in an analog-digital-converter, including: a receiving unit having a clock unit with a plurality of clock-driven switches for receiving an input signal; for each of the plurality of clock-driven switches, a first demultiplexer, for receiving the input signal via a clock-driven switch and for providing a number of first demultiplexer outputs; for a first demultiplexer output, at least one storage element for a stored input potential depending on the input signal; and an output demultiplexer for receiving an indication about the stored input potential and for outputting a corresponding sampling output signal to a respective sampling output.
摘要翻译：一种用于模拟数字转换器并用于提供采样输出信号和模拟 - 数字转换器的采样和交错级装置。一种用于模拟数字转换器的采样和交错级装置，包括：具有时钟单元的接收单元，具有用于接收输入信号的多个时钟驱动开关; 对于所述多个时钟驱动开关中的每一个，第一解复用器，用于经由时钟驱动开关接收所述输入信号，并用于提供多个第一解复用器输出; 对于第一解复用器输出，至少一个用于存储的输入电位的存储元件，取决于输入信号; 以及输出解复用器，用于接收关于所存储的输入电位的指示，并将对应的采样输出信号输出到相应的采样输出。

55. 发明授权

US09030344B2 System and method for integration of hybrid pipeline 有权
标题翻译：混合管道整合系统与方法
公开(公告)号：US09030344B2
公开(公告)日：2015-05-12
申请号：US14021735
申请日：2013-09-09
申请人： Broadcom Corporation
发明人： Chun-Ying Chen , Wei-Ta Shih , Rong Wu , Young Shin , Karthik Raviprakash , Tao Wang , Chia-Jen Hsu , Tianwei Li
IPC分类号： H03M1/12 , H03M1/00 , H03M1/06
CPC分类号： H03M1/187 , H03M1/00 , H03M1/0695 , H03M1/1215 , H03M1/144 , H03M1/164
摘要： A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.
摘要翻译：系统包括作为处理输入信号的第一级的流水线模数转换器和用于处理输入信号的逐次逼近寄存器（SAR）模数转换器作为第二级。 SAR模数转换器包括功率调整元件，用于调整SAR模数转换器的参考电压，以匹配流水线模数转换器的满量程电压。

56. 发明授权

US08988264B2 Analogue to digital converter 有权
标题翻译：模数转换器
公开(公告)号：US08988264B2
公开(公告)日：2015-03-24
申请号：US13780679
申请日：2013-02-28
申请人： NXP B.V.
发明人： Kyoohyun Noh , Jose de Jesus Pineda De Gyvez , Maarten Vertregt
IPC分类号： H03M1/12 , H03M1/00 , H03M1/60 , H03M1/06
CPC分类号： H03M1/002 , H03M1/0682 , H03M1/1215 , H03M1/60
摘要： An Analogue to Digital Converter (ADC) having a Gated Ring Voltage Controlled Oscillator, GRVCO, to generate a phase signal according to an input voltage; and a quantization circuit to generate a quantized phase output signal according. The GRVCO operates in either a first or second mode of operation according to a gating control signal. In the first mode of operation, the GRVCO operates in a VCO mode with gating disabled. In the second mode of operation, the GRVCO operates in a GRVCO mode wherein gating is enabled or disabled according to a gating signal.
摘要翻译：具有门控电压控制振荡器（GRVCO）的模数转换器（ADC），用于根据输入电压产生相位信号; 以及用于产生量化相位输出信号的量化电路。 GRVCO根据门控控制信号在第一或第二工作模式下工作。在第一种操作模式下，GRVCO在禁止门禁的VCO模式下工作。在第二种操作模式中，GRVCO在GRVCO模式下工作，其中根据门控信号启用或禁用门控。

57. 发明授权

US08981976B2 Analog-to-digital conversion with noise injection via wavefront multiplexing techniques 有权
标题翻译：通过波前复用技术进行噪声注入的模数转换
公开(公告)号：US08981976B2
公开(公告)日：2015-03-17
申请号：US13762413
申请日：2013-02-08
申请人： Donald C.D. Chang
发明人： Donald C. D. Chang , Tzer-Hso Lin , Yuanchang Liu
IPC分类号： H03M1/20 , H04B1/04 , H03M1/12 , H03M1/06 , H04B7/10
CPC分类号： H03M1/002 , H03M1/0641 , H03M1/08 , H03M1/12 , H03M1/1205 , H03M1/1215 , H03M1/188 , H03M1/20 , H04B1/0475 , H04B1/123 , H04B7/10 , H04L27/06
摘要： A novel noise injection technique is presented to improve dynamic range with low resolution and low speed analog to digital converters. This technique combines incoming signal and noise signal with wave front de-multiplexer and split into several channels. Then low resolution and low speed analog to digital converters are used to sample each channels. All signals are recovered using wave front multiplexer. For advanced design, ground diagnostic signals with optimizing processor can be added to guarantee recovery quality.
摘要翻译：提出了一种新颖的噪声注入技术，通过低分辨率和低速模数转换器来改善动态范围。该技术将输入信号和噪声信号与波前解复用器相结合，并分为多个通道。然后使用低分辨率和低速模数转换器对每个通道进行采样。所有信号使用波前复用器进行恢复。对于先进的设计，可以添加具有优化处理器的接地诊断信号，以保证恢复质量。

58. 再颁专利

USRE45343E1 Calibration of offset gain and phase errors in M-channel time-interleaved analog-to-digital converters 有权
标题翻译： M通道时间交替模数转换器中偏移增益和相位误差的校准
公开(公告)号：USRE45343E1
公开(公告)日：2015-01-20
申请号：US13683139
申请日：2012-11-21
申请人： Intersil Americas Inc.
发明人： Sundar S. Kidambi
IPC分类号： H03M1/06
CPC分类号： H03M1/06 , H03M1/0624 , H03M1/1028 , H03M1/1215 , H04B1/16
摘要： Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). In order to obtain an error measure for offset, gain or phase, errors, outputs from each ADC are either summed or averaged over No samples. Calling each of the sums or averages as Xk where k=1, 2, . . . , M, there are M such values as a result. A single value representing the mean of these M values, Xmean, is chosen as a reference value. The offset, gain and phase errors for the M different ADCs are then obtained from Xk−Xmean. The sign of each offset error, i.e., sign (Xk−Xmean), is then used to drive an adaptive algorithm whose output represents an offset correction value for the corresponding ADC. The offset, gain, and phase correction outputs from the adaptive algorithm is fed to an array of Digital-to-Analog converters (DACs) whose outputs are voltages or currents that directly or indirectly controls the offset, gain or phase setting of each individual ADC. Thus, there are M different offset, gain and phase error signals and M different adaptive algorithms operating in conjunction with M different DACs providing offset control signals to M different ADCs. In certain embodiments, spur frequencies can be reduced with the use of notch filters.
摘要翻译：用于校正M通道时间交织模数转换器（ADC）中元件失配的技术。为了获得偏移，增益或相位误差的误差，错误，每个ADC的输出在无样本之间求和或平均。将每个或者平均值调用为X k，其中k = 1,2。。。，M，结果有这样的M值。选择表示这些M值的平均值的单个值Xmean作为参考值。然后从Xk-Xmean获得M个不同ADC的偏移，增益和相位误差。然后使用每个偏移误差的符号，即符号（Xk-Xmean）来驱动自适应算法，其自适应算法的输出表示对应的ADC的偏移校正值。来自自适应算法的偏移，增益和相位校正输出被馈送到数模转换器（DAC）阵列，数字模拟转换器（DAC）的输出是直接或间接控制每个ADC的偏移，增益或相位设置的电压或电流。因此，存在M个不同的偏移，增益和相位误差信号，以及M个不同的自适应算法，与M个不同的DAC结合，为M个不同的ADC提供偏移控制信号。在某些实施例中，使用陷波滤波器可以减少杂散频率。

59. 发明申请

US20150015428A1 SYSTEM AND METHOD FOR HIGH SPEED ANALOG TO DIGITAL DATA ACQUISITION 有权
标题翻译：用于高速模拟数字数据采集的系统和方法
公开(公告)号：US20150015428A1
公开(公告)日：2015-01-15
申请号：US14334919
申请日：2014-07-18
申请人： KAPIK INC.
发明人： William Martin SNELGROVE
IPC分类号： H03M1/12 , H03M1/06
CPC分类号： H03M1/1245 , H03M1/0626 , H03M1/0631 , H03M1/0639 , H03M1/12 , H03M1/1215 , H03M3/458
摘要： An analog to digital conversion system is disclosed which converts an analog signal to a digital representation thereof at a first sampling rate by distributing the analog signal to at least two signal paths, at least one signal path including a limiting mixer to mix the signal with a respective selected square wave and a smoothing (low pass) filter to filter the mixed signal before providing the mixed and filtered signal to a subconverter, the subconverter having a sampling rate less than the first sampling rate, and a digital matrix filter to combine the digital output of each subconverter to form a digital representation of the analog signal as sampled at the first rate.
摘要翻译：公开了一种模数转换系统，其通过将模拟信号分配到至少两个信号路径将模拟信号转换成其第一采样率的数字表示，至少一个信号路径包括限制混频器以将信号与相应选择的方波和平滑（低通）滤波器，以在将混合和滤波的信号提供给子转换器之前对混合信号进行滤波，该子转换器具有小于第一采样率的采样率，以及数字矩阵滤波器，以将数字每个子转换器的输出以形成以第一速率采样的模拟信号的数字表示。

60. 再颁专利

USRE45282E1 Method and apparatus for operating a CMOS imager having a pipelined analog to digital converter 有权
标题翻译：用于操作具有流水线模数转换器的CMOS成像器的方法和装置
公开(公告)号：USRE45282E1
公开(公告)日：2014-12-09
申请号：US13357118
申请日：2012-01-24
申请人： Eric R. Fossum , Sandor L. Barna
发明人： Eric R. Fossum , Sandor L. Barna
IPC分类号： H03M1/34
CPC分类号： H03M1/18 , H03M1/1215 , H03M1/46
摘要： An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available. A system includes a CMOS active pixel image sensor having an array for photoreceptors to convert an image into an analog signal. The CMOS image sensor converts the analog signal into a digital signal using a pipelined analog to digital converter.
摘要翻译：使用偏移模数转换器的图像传感器系统。模数转换器需要多个时钟周期来执行实际的转换。这些转换在时间上彼此偏移，因此在每个时钟周期，新的数据可用。一种系统包括具有用于将图像转换为模拟信号的感光体的阵列的CMOS有源像素图像传感器。 CMOS图像传感器使用流水线模数转换器将模拟信号转换为数字信号。

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