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51. 发明授权

US09337257B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09337257B2
公开(公告)日：2016-05-10
申请号：US14398334
申请日：2013-05-10
申请人： ROHM CO., LTD.
发明人： Yuki Nakano , Hiroyuki Sakairi
IPC分类号： H01L29/00 , H01L29/06 , H01L29/20 , H01L29/16 , H01L29/417 , H01L29/78 , H01L29/04
CPC分类号： H01L29/0646 , H01L21/046 , H01L29/045 , H01L29/0619 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/41741 , H01L29/41775 , H01L29/7811
摘要： [Problem] To provide a semiconductor device in which it is possible to lessen the local concentration of an electric field on a termination structure.[Solution] The semiconductor device (1) comprises: an n-type SiC substrate (2) having an active region (3); a p-type termination structure (4) formed along the outer periphery of the active region (3), and a source electrode (14) that is formed on the SiC substrate (2) with an interlayer film (12) therebetween, and that selectively penetrates the interlayer film (12) and is connected to the termination structure (4). The termination structure (4) forms a second side (42) that has a relatively high dielectric breakdown strength, and a first side (41) that has a relatively low dielectric breakdown strength compared to the second side (42). The shape of the second side (42) and the shape of the first side (41) are asymmetrical.
摘要翻译：本发明提供一种半导体器件，其中可以减小终端结构上电场的局部浓度。 [解决方案]半导体器件（1）包括：具有有源区（3）的n型SiC衬底（2）沿着有源区（3）的外周形成的p型端接结构（4）和在其上具有中间膜（12）的SiC衬底（2）上形成的源电极（14），并且选择性地穿透层间膜（12）并连接到终端结构（4）。终端结构（4）形成具有相对较高的介电击穿强度的第二侧（42）和与第二侧（42）相比具有相对较低介电击穿强度的第一侧面（41）。第二侧（42）的形状和第一侧（41）的形状是不对称的。

52. 发明授权

US09324782B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09324782B2
公开(公告)日：2016-04-26
申请号：US14344195
申请日：2012-11-09
申请人： Naruhisa Miura , Shiro Hino , Kenichi Ohtsuka
发明人： Naruhisa Miura , Shiro Hino , Kenichi Ohtsuka
IPC分类号： H01L29/06 , H01L29/12 , H01L29/66 , H01L29/78 , H01L29/10 , H01L29/16 , H01L29/20
CPC分类号： H01L29/66712 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/66045 , H01L29/66068 , H01L29/7811
摘要： A semiconductor layer, a well region, and a source region form a unit cell. The unit cell is defined into a certain shape in plan view at a main surface of the semiconductor layer, and a plurality of the unit cells is coupled in a chain manner to form a unit chain structure with a constriction. The certain shape of the unit cell is defined by an outer edge of a virtual region of the semiconductor layer defined so as to include the source region and the well region inside and by respective outer edges of the source region and the well region at a joint with a different unit cell. An active region is composed of a plurality of the unit chain structures. The unit chain structures are arranged so as to avoid generation of a gap between the unit cells of adjacent ones of the unit chain structures.
摘要翻译：半导体层，阱区和源极区形成单元。单元电池在半导体层的主表面的平面图中被限定为一定的形状，并且多个单元电池以链状的方式耦合以形成具有缩小的单位链结构。单元电池的特定形状由半导体层的虚拟区域的外边缘限定，以便包括源极区域和阱区域以及源极区域和在接合处的阱区域的相应外边缘与不同的单元格。有源区域由多个单位链结构组成。单元链结构被布置为避免在相邻单元链结构的单元电池之间产生间隙。

53. 发明授权

US09318547B2 Wide bandgap insulated gate semiconductor device 有权
公开(公告)号：US09318547B2
公开(公告)日：2016-04-19
申请号：US14744297
申请日：2015-06-19
申请人： Fuji Electric Co., Ltd.
发明人： Naoki Kumagai
IPC分类号： H01L29/15 , H01L31/0256 , H01L29/66 , H01L29/06 , H01L29/739 , H01L29/16 , H01L29/20 , H01L29/417 , H01L29/78 , H01L29/08 , H01L29/10
CPC分类号： H01L29/0615 , H01L29/0623 , H01L29/0878 , H01L29/1095 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/41741 , H01L29/41766 , H01L29/7395 , H01L29/7397 , H01L29/7802 , H01L29/7813
摘要： A wide bandgap insulated gate semiconductor device includes a semiconductor substrate made of semiconductor having a bandgap wider than silicon; n− drift layer over the semiconductor substrate; p-channel regions selectively disposed over the drift layer; n+ semiconductor regions selectively disposed in respective surfaces in the channel regions; a plurality of p+ base regions in contact with bottoms of the respective channel regions; a protruding drift layer portion that is n-type region interposed between the p-channel regions and the p+ base regions thereunder; a gate electrode formed, through a gate insulating film, on the protruding drift layer portion and on respective surfaces of the p-channel regions; a source electrode in contact with the n+ semiconductor regions in the channel regions; and a p+ floating region inside the protruding drift layer portion, having side faces respectively facing side faces of the second conductivity type base regions, wherein respective gaps between the p+ base regions and the p+ floating region defined by the respective side faces have a wide portion and a narrow portion.

54. 发明授权

US09293543B2 Film forming method and film forming apparatus 有权
标题翻译：成膜方法和成膜装置
公开(公告)号：US09293543B2
公开(公告)日：2016-03-22
申请号：US14044119
申请日：2013-10-02
申请人： TOKYO ELECTRON LIMITED , OSAKA UNIVERSITY
发明人： Shuji Azumo , Yusaku Kashiwagi , Yuichiro Morozumi , Yu Wamura , Katsushige Harada , Kosuke Takahashi , Heiji Watanabe , Takayoshi Shimura , Takuji Hosoi
IPC分类号： H01L21/283 , H01L21/441 , H01L29/51 , H01L29/40 , H01L21/04 , H01L21/28 , H01L21/02 , C23C16/30 , H01L29/66 , H01L29/78 , H01L29/16 , H01L29/20
CPC分类号： H01L29/401 , C23C16/303 , C23C16/308 , H01L21/02178 , H01L21/022 , H01L21/02252 , H01L21/02271 , H01L21/0228 , H01L21/02326 , H01L21/02332 , H01L21/044 , H01L21/049 , H01L21/28264 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66045 , H01L29/66068 , H01L29/66712 , H01L29/66734 , H01L29/7802 , H01L29/7813
摘要： Provided is a method of forming a gate insulating film for use in a MOSFET for a power device. An AlN film is formed on a SiC substrate of a wafer W and then the formation of an AlO film and the formation of an AlN film on the formed AlO film are repeated, thereby forming an AlON film having a laminated structure in which AlO films and AlN films are alternately laminated. A heat treatment is performed on the AlON film having the laminated structure.
摘要翻译：提供一种形成用于功率器件的MOSFET的栅极绝缘膜的方法。在晶片W的SiC衬底上形成AlN膜，然后重复形成AlO膜并在AlO膜上形成AlN膜，从而形成具有层叠结构的AlON膜，其中AlO膜和 AlN膜交替层压。对具有层叠结构的AlON膜进行热处理。

55. 发明申请

US20160079142A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160079142A1
公开(公告)日：2016-03-17
申请号：US14888009
申请日：2013-05-29
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： Shigeru HASEGAWA , Kazuhiro MORISHITA , Ryo TSUDA , Yukimasa HAYASHIDA , Goro YASUTOMI , Ryutaro DATE
IPC分类号： H01L23/367 , H01L23/498 , H01L29/16 , H01L25/07 , H01L29/20 , H01L23/492 , H01L23/40
CPC分类号： H01L23/3675 , H01L23/3735 , H01L23/4006 , H01L23/492 , H01L23/49811 , H01L23/49838 , H01L25/072 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L2023/4087 , H01L2224/48091 , H01L2224/48137 , H01L2924/13055 , H01L2924/00014 , H01L2924/00
摘要： A base plate, and a plurality of unit structures formed on the base plate are provided. Each of the unit structures including an insulating substrate fixed on the base plate, a metal pattern formed on the insulating substrate, a semiconductor element electrically connected to the metal pattern, and a main electrode having an upper end portion exposed to the outside and a lower end portion connected to a peripheral portion of the metal pattern closest to an outer edge of the base plate.
摘要翻译：提供基板和形成在基板上的多个单元结构。每个单元结构包括固定在基板上的绝缘基板，形成在绝缘基板上的金属图案，与金属图案电连接的半导体元件和具有暴露于外部的上端部的主电极和下部连接到最靠近基板的外边缘的金属图案的周边部分的端部。

56. 发明申请

US20160056152A1 MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURE 审中-公开
标题翻译：多层半导体器件结构
公开(公告)号：US20160056152A1
公开(公告)日：2016-02-25
申请号：US14933096
申请日：2015-11-05
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： YASUTOSHI OKUNO , YI-TANG LIN
IPC分类号： H01L27/06 , H01L29/20 , H01L27/092 , H01L29/16 , H01L27/12 , H01L23/544
CPC分类号： H01L27/0688 , G03F7/70633 , G03F9/7073 , G03F9/708 , H01L21/8234 , H01L23/544 , H01L27/092 , H01L27/1207 , H01L29/16 , H01L29/1602 , H01L29/1608 , H01L29/20 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening.
摘要翻译：本公开的一个实施例提供一种半导体结构，其包括：第一器件层，包括设置在衬底上的第一有源层和设置在有源层上的第一栅极层，其中第一有源层和第一栅极中的至少一个层包括第一层对准结构; 设置在所述第一器件层上的第一界限层，所述第一界限层包括布置成可检测地暴露所述第一层对准结构的开口; 以及设置在所述界限层上方的第二器件层，包括第二层对准结构，其中所述第二层对准结构通过所述开口基本对准所述第一层对准结构。

57. 发明申请

US20160027737A1 Stretchable Form of Single Crystal Silicon for High Performance Electronics on Rubber Substrates 有权
公开(公告)号：US20160027737A1
公开(公告)日：2016-01-28
申请号：US14789645
申请日：2015-07-01
申请人： The Board of Trustees of the University of Illinois
发明人： John A. ROGERS , Dahl-Young KHANG , Yugang SUN , Etienne MENARD
IPC分类号： H01L23/538 , H05K1/02 , H01L29/786 , H01L23/00
CPC分类号： H01L23/5387 , B81C2201/0185 , B82Y10/00 , H01L21/02422 , H01L21/02521 , H01L21/02532 , H01L21/02546 , H01L21/02628 , H01L21/6835 , H01L23/293 , H01L23/3157 , H01L23/564 , H01L24/29 , H01L24/32 , H01L24/80 , H01L27/1266 , H01L27/1285 , H01L27/1292 , H01L29/06 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/151 , H01L29/158 , H01L29/16 , H01L29/1602 , H01L29/1606 , H01L29/7781 , H01L29/78603 , H01L29/78681 , H01L29/78696 , H01L31/0392 , H01L31/03925 , H01L31/03926 , H01L31/18 , H01L31/1804 , H01L2221/68368 , H01L2224/291 , H01L2224/2919 , H01L2224/80894 , H01L2224/8385 , H01L2924/0002 , H01L2924/01002 , H01L2924/01003 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01051 , H01L2924/01067 , H01L2924/01072 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/07802 , H01L2924/10329 , H01L2924/10336 , H01L2924/10349 , H01L2924/12032 , H01L2924/12036 , H01L2924/12041 , H01L2924/12042 , H01L2924/13063 , H01L2924/13091 , H01L2924/1461 , H01L2924/3025 , H05K1/0277 , H05K1/0283 , Y02E10/547 , Y02P70/521 , H01L2924/3512 , H01L2924/00 , H01L2924/00014
摘要： The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

58. 发明申请

US20160013137A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20160013137A1
公开(公告)日：2016-01-14
申请号：US14712354
申请日：2015-05-14
申请人： Sumitomo Electric Industries, Ltd.
发明人： Toru HIYOSHI , Taku HORII
IPC分类号： H01L23/00 , H01L21/02 , H01L21/78 , H01L21/3205 , H01L29/16 , H01L29/20
CPC分类号： H01L23/562 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/0485 , H01L21/32051 , H01L21/561 , H01L21/78 , H01L23/3192 , H01L23/585 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/66068 , H01L29/7395 , H01L29/7811 , H01L2224/04042 , H01L2224/05558 , H01L2224/06181 , H01L2224/94 , H01L2224/03
摘要： A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor layer including a wide bandgap semiconductor, the semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of the element region when viewed two-dimensionally, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The step portion has a sidewall recessed downward from a main surface of the element region in a cross section parallel to a thickness direction of the semiconductor layer, and the metal layer extends to cover at least a portion of the sidewall. The method of manufacturing a semiconductor device further includes the step of dividing the semiconductor layer into the element regions on an outside of the step portion when viewed from the element region.
摘要翻译：一种制造半导体器件的方法包括以下步骤：制造包括宽带隙半导体的半导体层，半导体层具有元件区域和围绕元件区域的外周的外周区域，二维地观察，形成步骤围绕所述外周区域中的所述元件区域的外周的部分，以及沿着所述台阶部形成金属层。台阶部分具有从与半导体层的厚度方向平行的截面从元件区域的主表面向下凹陷的侧壁，并且金属层延伸以覆盖侧壁的至少一部分。半导体器件的制造方法还包括当从元件区域观察时，将半导体层分割成台阶部分的外侧的元件区域的步骤。

59. 发明申请

US20150333120A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150333120A1
公开(公告)日：2015-11-19
申请号：US14398334
申请日：2013-05-10
申请人： ROHM CO., LTD.
发明人： Yuki NAKANO , Hiroyuki SAKAIRI
IPC分类号： H01L29/06 , H01L29/16 , H01L29/04 , H01L29/20
CPC分类号： H01L29/0646 , H01L21/046 , H01L29/045 , H01L29/0619 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/41741 , H01L29/41775 , H01L29/7811
摘要： [Problem] To provide a semiconductor device in which it is possible to lessen the local concentration of an electric field on a termination structure.[Solution] The semiconductor device (1) comprises: an n-type SiC substrate (2) having an active region (3); a p-type termination structure (4) formed along the outer periphery of the active region (3), and a source electrode (14) that is formed on the SiC substrate (2) with an interlayer film (12) therebetween, and that selectively penetrates the interlayer film (12) and is connected to the termination structure (4). The termination structure (4) forms a second side (42) that has a relatively high dielectric breakdown strength, and a first side (41) that has a relatively low dielectric breakdown strength compared to the second side (42). The shape of the second side (42) and the shape of the first side (41) are asymmetrical.
摘要翻译：本发明提供一种半导体器件，其中可以减小终端结构上电场的局部浓度。 [解决方案]半导体器件（1）包括：具有有源区（3）的n型SiC衬底（2）沿着有源区（3）的外周形成的p型端接结构（4）和在其上具有中间膜（12）的SiC衬底（2）上形成的源电极（14），并且选择性地穿透层间膜（12）并连接到终端结构（4）。终端结构（4）形成具有相对较高的介电击穿强度的第二侧（42）和与第二侧（42）相比具有相对较低介电击穿强度的第一侧面（41）。第二侧（42）的形状和第一侧（41）的形状是不对称的。

60. 发明授权

US09184286B2 Semiconductor device having a breakdown voltage holding region 有权
标题翻译：具有击穿电压保持区域的半导体器件
公开(公告)号：US09184286B2
公开(公告)日：2015-11-10
申请号：US13983157
申请日：2012-02-01
申请人： Yuki Nakano
发明人： Yuki Nakano
IPC分类号： H01L29/66 , H01L29/78 , H01L21/82 , H01L29/417 , H01L29/06 , H01L29/10 , H01L29/16 , H01L29/45 , H01L29/47 , H01L29/20
CPC分类号： H01L29/7813 , H01L21/8213 , H01L27/088 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/086 , H01L29/1095 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/41766 , H01L29/45 , H01L29/47 , H01L29/66045 , H01L29/66068 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7827 , H01L2224/0603
摘要： A semiconductor device of the present invention is a semiconductor device having a semiconductor layer comprising a wide band gap semiconductor, wherein the semiconductor layer includes: a first conductivity-type source region, a second conductivity-type channel region and a first conductivity-type drain region, which are formed in this order from the surface side of the semiconductor layer; a source trench lying from the surface of the semiconductor layer through the source region and the channel region to the drain region; a gate insulating film formed so as to contact the channel region; a gate electrode facing the channel region with the gate insulating film interposed therebetween; and a first breakdown voltage holding region of a second conductivity type formed selectively on the side face or the bottom face of the source trench, and the semiconductor device includes a barrier formation layer, which is joined with the drain region in the source trench, for forming, by junction with the drain region, a junction barrier lower than a diffusion potential of a body diode formed by p-n junction between the channel region and the drain region.
摘要翻译：本发明的半导体器件是具有包括宽带隙半导体的半导体层的半导体器件，其中半导体层包括：第一导电型源极区，第二导电型沟道区和第一导电类型漏极区域，其从半导体层的表面侧依次形成; 源极沟槽，其从半导体层的表面通过源极区域和沟道区域到达漏极区域; 形成为与沟道区域接触的栅极绝缘膜; 面对沟道区域的栅电极，其间插入有栅极绝缘膜; 以及选择性地形成在源沟槽的侧面或底面上的第二导电类型的第一击穿电压保持区域，并且所述半导体器件包括与源极沟槽中的漏极区域接合的势垒形成层，用于通过与漏极区域的连接形成低于由沟道区域和漏极区域之间的pn结形成的体二极管的扩散电位的结屏障。

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